51 #define NREGS_EXT_DMA (0x80/sizeof(uint32_t)) 52 #define NREGS_MISC (0x80/sizeof(uint32_t)) 67 #define EXTDMA_CTRL_EXT_ADDR 0x00 68 #define EXTDMA_CTRL_SH4_ADDR 0x04 69 #define EXTDMA_CTRL_SIZE 0x08 70 #define EXTDMA_CTRL_DIR 0x0c 71 #define EXTDMA_CTRL_MODE 0x10 72 #define EXTDMA_CTRL_CHAN_ENABLE 0x14 73 #define EXTDMA_CTRL_XFER_ENABLE 0x18 74 #define EXTDMA_CTRL_STATUS 0x1c 76 #define EXTDMA_WAITSTATE 0x90 77 #define EXTDMA_MAGIC 0xbc 78 #define EXTDMA_MAGIC_VALUE 0x4659404f 79 #define EXTDMA_MAGIC_VALUE_ROM 0x46597f00 81 #define EXTDMA_STAT_EXT_ADDR 0xc0 82 #define EXTDMA_STAT_SH4_ADDR 0xc4 83 #define EXTDMA_STAT_SIZE 0xc8 84 #define EXTDMA_STAT_STATUS 0xcc 90 uint64_t idata = 0, odata = 0;
91 int reg = relative_addr, channel = 0;
98 odata = d->
extdma_reg[relative_addr /
sizeof(uint32_t)];
112 channel = (reg >> 5) & 3;
115 if (reg >= 0xc0 && reg < 0xff) {
116 channel = (reg >> 4) & 3;
117 reg = 0xc0 + (reg & 0xf);
124 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 125 " EXT_ADDR = 0x%08x ]\n", channel, (
int) idata);
131 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 132 " SH4_ADDR = 0x%08x ]\n", channel, (
int) idata);
138 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 139 " SIZE = 0x%08x ]\n", channel, (
int) idata);
145 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 146 " DIR = 0x%08x ]\n", channel, (
int) idata);
152 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 153 " MODE = 0x%08x ]\n", channel, (
int) idata);
159 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 160 " CHAN_ENABLE = 0x%08x ]\n", channel, (
int) idata);
162 fatal(
"EXTDMA_CTRL_CHAN_ENABLE: todo\n");
170 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 171 " XFER_ENABLE = 0x%08x ]\n", channel, (
int) idata);
173 fatal(
"EXTDMA_CTRL_XFER_ENABLE: todo\n");
181 debug(
"[ dreamcast_g2_extdma: write to channel %i:" 182 " STATUS = 0x%08x ]\n", channel, (
int) idata);
184 fatal(
"[ dreamcast_g2_extdma: write to channel %i:" 185 " STATUS = 0x%08x: TODO (start transfer?) ]\n",
186 channel, (
int) idata);
212 fatal(
"Unimplemented g2 extdma magic " 213 "vaule 0x%x\n", (
int) idata);
219 default:
if (writeflag ==
MEM_READ) {
220 fatal(
"[ dreamcast_g2_extdma: read from addr 0x%x ]\n",
223 fatal(
"[ dreamcast_g2_extdma: write to addr 0x%x: " 224 "0x%x ]\n", (
int)relative_addr, (
int)idata);
232 d->
extdma_reg[relative_addr /
sizeof(uint32_t)] = idata;
244 uint64_t idata = 0, odata = 0;
251 odata = d->
misc_reg[relative_addr /
sizeof(uint32_t)];
253 switch (relative_addr) {
257 if (writeflag !=
MEM_WRITE || idata != 0x1fffff) {
258 fatal(
"[ dreamcast_g2_misc: unimplemented 0xe4 ]\n");
263 default:
if (writeflag ==
MEM_READ) {
264 debug(
"[ dreamcast_g2_misc: read from addr 0x%x ]\n",
267 debug(
"[ dreamcast_g2_misc: write to addr 0x%x: " 268 "0x%x ]\n", (
int)relative_addr, (
int)idata);
276 d->
misc_reg[relative_addr /
sizeof(uint32_t)] = idata;
295 0x80, dev_dreamcast_g2_misc_access, d,
DM_DEFAULT, NULL);
298 0x100, dev_dreamcast_g2_extdma_access, d,
DM_DEFAULT, NULL);
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void fatal(const char *fmt,...)
#define EXTDMA_CTRL_STATUS
#define EXTDMA_CTRL_CHAN_ENABLE
#define EXTDMA_MAGIC_VALUE_ROM
#define EXTDMA_CTRL_EXT_ADDR
#define EXTDMA_MAGIC_VALUE
#define CHECK_ALLOCATION(ptr)
DEVICE_ACCESS(dreamcast_g2_extdma)
uint32_t extdma_reg[NREGS_EXT_DMA]
uint32_t misc_reg[NREGS_MISC]
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
#define EXTDMA_CTRL_XFER_ENABLE
#define EXTDMA_CTRL_SH4_ADDR