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Macros | |
#define | COP0_NAMES |
#define | COP0_INDEX 0 |
#define | INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */ |
#define | INDEX_MASK 0x3f |
#define | R2K3K_INDEX_P 0x80000000UL |
#define | R2K3K_INDEX_MASK 0x3f00 |
#define | R2K3K_INDEX_SHIFT 8 |
#define | COP0_RANDOM 1 |
#define | RANDOM_MASK 0x3f |
#define | R2K3K_RANDOM_MASK 0x3f00 |
#define | R2K3K_RANDOM_SHIFT 8 |
#define | COP0_ENTRYLO0 2 |
#define | COP0_ENTRYLO1 3 |
#define | ENTRYLO_PFN_MASK 0x3fffffc0 |
#define | ENTRYLO_PFN_SHIFT 6 |
#define | ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */ |
#define | ENTRYLO_C_SHIFT 3 |
#define | ENTRYLO_D 0x04 /* Dirty bit */ |
#define | ENTRYLO_V 0x02 /* Valid bit */ |
#define | ENTRYLO_G 0x01 /* Global bit */ |
#define | R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL |
#define | R2K3K_ENTRYLO_PFN_SHIFT 12 |
#define | R2K3K_ENTRYLO_N 0x800 |
#define | R2K3K_ENTRYLO_D 0x400 |
#define | R2K3K_ENTRYLO_V 0x200 |
#define | R2K3K_ENTRYLO_G 0x100 |
#define | COP0_CONTEXT 4 |
#define | CONTEXT_BADVPN2_MASK 0x007ffff0 |
#define | CONTEXT_BADVPN2_MASK_R4100 0x01fffff0 |
#define | CONTEXT_BADVPN2_SHIFT 4 |
#define | R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc |
#define | R2K3K_CONTEXT_BADVPN_SHIFT 2 |
#define | COP0_PAGEMASK 5 |
#define | PAGEMASK_MASK 0x01ffe000 |
#define | PAGEMASK_SHIFT 13 |
#define | PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
#define | PAGEMASK_SHIFT_R4100 11 |
#define | COP0_WIRED 6 |
#define | COP0_RESERV7 7 |
#define | COP0_BADVADDR 8 |
#define | COP0_COUNT 9 |
#define | COP0_ENTRYHI 10 |
#define | ENTRYHI_R_MASK 0xc000000000000000ULL |
#define | ENTRYHI_R_XKPHYS 0x8000000000000000ULL |
#define | ENTRYHI_R_SHIFT 62 |
#define | ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
#define | ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
#define | ENTRYHI_VPN2_SHIFT 13 |
#define | ENTRYHI_ASID 0xff |
#define | TLB_G (1 << 12) |
#define | R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL |
#define | R2K3K_ENTRYHI_VPN_SHIFT 12 |
#define | R2K3K_ENTRYHI_ASID_MASK 0xfc0 |
#define | R2K3K_ENTRYHI_ASID_SHIFT 6 |
#define | COP0_COMPARE 11 |
#define | COP0_STATUS 12 |
#define | STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */ |
#define | STATUS_CU_SHIFT 28 |
#define | STATUS_RP 0x08000000 /* reduced power */ |
#define | STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */ |
#define | STATUS_RE 0x02000000 /* reverse endian bit */ |
#define | STATUS_BEV 0x00400000 /* boot exception vectors (?) */ |
#define | STATUS_IM_MASK 0xff00 |
#define | STATUS_IM_SHIFT 8 |
#define | STATUS_KX 0x80 |
#define | STATUS_SX 0x40 |
#define | STATUS_UX 0x20 |
#define | STATUS_KSU_MASK 0x18 |
#define | STATUS_KSU_SHIFT 3 |
#define | STATUS_ERL 0x04 |
#define | STATUS_EXL 0x02 |
#define | STATUS_IE 0x01 |
#define | R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */ |
#define | R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */ |
#define | COP0_CAUSE 13 |
#define | CAUSE_BD 0x80000000UL /* branch delay flag */ |
#define | CAUSE_CE_MASK 0x30000000 /* which coprocessor */ |
#define | CAUSE_CE_SHIFT 28 |
#define | CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */ |
#define | CAUSE_WP 0x00400000UL /* watch exception ... */ |
#define | CAUSE_IP_MASK 0xff00 /* interrupt pending */ |
#define | CAUSE_IP_SHIFT 8 |
#define | CAUSE_EXCCODE_MASK 0x7c /* exception code */ |
#define | R2K3K_CAUSE_EXCCODE_MASK 0x3c |
#define | CAUSE_EXCCODE_SHIFT 2 |
#define | COP0_EPC 14 |
#define | COP0_PRID 15 |
#define | COP0_CONFIG 16 |
#define | COP0_LLADDR 17 |
#define | COP0_WATCHLO 18 |
#define | COP0_WATCHHI 19 |
#define | COP0_XCONTEXT 20 |
#define | XCONTEXT_R_MASK 0x180000000ULL |
#define | XCONTEXT_R_SHIFT 31 |
#define | XCONTEXT_BADVPN2_MASK 0x7ffffff0 |
#define | XCONTEXT_BADVPN2_SHIFT 4 |
#define | COP0_FRAMEMASK 21 /* R10000 */ |
#define | COP0_RESERV22 22 |
#define | COP0_DEBUG 23 |
#define | COP0_DEPC 24 |
#define | COP0_PERFCNT 25 |
#define | COP0_ERRCTL 26 |
#define | COP0_CACHEERR 27 |
#define | COP0_TAGDATA_LO 28 |
#define | COP0_TAGDATA_HI 29 |
#define | COP0_ERROREPC 30 |
#define | COP0_DESAVE 31 |
#define | COP1_REVISION 0 |
#define | COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */ |
#define | COP1_REVISION_PS 0x40000 /* Paired-single support */ |
#define | COP1_REVISION_DOUBLE 0x20000 /* double precision support */ |
#define | COP1_REVISION_SINGLE 0x10000 /* single precision support */ |
#define | COP1_CONTROLSTATUS 31 |
#define | KSU_KERNEL 0 |
#define | KSU_SUPERVISOR 1 |
#define | KSU_USER 2 |
#define | EXCEPTION_NAMES |
#define | EXCEPTION_INT 0 /* Interrupt */ |
#define | EXCEPTION_MOD 1 /* TLB modification exception */ |
#define | EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */ |
#define | EXCEPTION_TLBS 3 /* TLB exception (store) */ |
#define | EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */ |
#define | EXCEPTION_ADES 5 /* Address Error Exception (store) */ |
#define | EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */ |
#define | EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */ |
#define | EXCEPTION_SYS 8 /* Syscall */ |
#define | EXCEPTION_BP 9 /* Breakpoint */ |
#define | EXCEPTION_RI 10 /* Reserved instruction */ |
#define | EXCEPTION_CPU 11 /* CoProcessor Unusable */ |
#define | EXCEPTION_OV 12 /* Arithmetic Overflow */ |
#define | EXCEPTION_TR 13 /* Trap exception */ |
#define | EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
#define | EXCEPTION_FPE 15 /* Floating point exception */ |
#define | EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
#define | EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ |
#define | EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */ |
#define | EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */ |
#define | EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */ |
#define | EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */ |
#define CAUSE_EXCCODE_MASK 0x7c /* exception code */ |
Definition at line 137 of file cop0.h.
Referenced by mips_unaligned_loadstore().
#define CAUSE_EXCCODE_SHIFT 2 |
Definition at line 139 of file cop0.h.
Referenced by mips_unaligned_loadstore().
#define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */ |
#define CONTEXT_BADVPN2_MASK 0x007ffff0 |
Definition at line 78 of file cop0.h.
Referenced by coproc_register_write().
#define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0 |
Definition at line 79 of file cop0.h.
Referenced by coproc_register_write().
#define COP0_BADVADDR 8 |
Definition at line 91 of file cop0.h.
Referenced by coproc_register_read(), and coproc_register_write().
#define COP0_CACHEERR 27 |
Definition at line 157 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_CAUSE 13 |
Definition at line 129 of file cop0.h.
Referenced by coproc_register_read(), mips_cpu_interrupt_assert(), mips_cpu_interrupt_deassert(), mips_unaligned_loadstore(), and X().
#define COP0_COMPARE 11 |
Definition at line 108 of file cop0.h.
Referenced by coproc_register_read(), and coproc_register_write().
#define COP0_CONFIG 16 |
Definition at line 142 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_CONTEXT 4 |
Definition at line 77 of file cop0.h.
Referenced by coproc_register_read(), and coproc_register_write().
#define COP0_COUNT 9 |
Definition at line 92 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), and X().
#define COP0_DEBUG 23 |
Definition at line 153 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_DESAVE 31 |
Definition at line 161 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_ENTRYHI 10 |
Definition at line 93 of file cop0.h.
Referenced by coproc_register_read(), coproc_tlbpr(), coproc_tlbwri(), and TRANSLATE_ADDRESS().
#define COP0_ENTRYLO0 2 |
Definition at line 60 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbpr(), and coproc_tlbwri().
#define COP0_ENTRYLO1 3 |
Definition at line 61 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbpr(), and coproc_tlbwri().
#define COP0_EPC 14 |
Definition at line 140 of file cop0.h.
Referenced by coproc_eret(), coproc_register_read(), and X().
#define COP0_ERRCTL 26 |
Definition at line 156 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_ERROREPC 30 |
Definition at line 160 of file cop0.h.
Referenced by coproc_eret(), coproc_register_read(), and X().
#define COP0_INDEX 0 |
Definition at line 50 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), and mips_cpu_tlbdump().
#define COP0_LLADDR 17 |
Definition at line 143 of file cop0.h.
Referenced by coproc_register_read(), and X().
#define COP0_NAMES |
#define COP0_PAGEMASK 5 |
Definition at line 83 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), and mips_coproc_new().
#define COP0_PERFCNT 25 |
Definition at line 155 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_PRID 15 |
Definition at line 141 of file cop0.h.
Referenced by coproc_register_read(), and mips_coproc_new().
#define COP0_RANDOM 1 |
Definition at line 56 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbwri(), and mips_cpu_tlbdump().
#define COP0_RESERV22 22 |
Definition at line 152 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_STATUS 12 |
Definition at line 109 of file cop0.h.
Referenced by cop0_availability_check(), coproc_eret(), coproc_register_read(), coproc_tlbwri(), memory_cache_R3000(), MEMORY_RW(), mips_coproc_new(), mips_cpu_new(), netbsd_r3k_cache_inv(), TRANSLATE_ADDRESS(), and X().
#define COP0_TAGDATA_HI 29 |
Definition at line 159 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_TAGDATA_LO 28 |
Definition at line 158 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_WATCHHI 19 |
Definition at line 145 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_WATCHLO 18 |
Definition at line 144 of file cop0.h.
Referenced by coproc_register_read().
#define COP0_WIRED 6 |
Definition at line 89 of file cop0.h.
Referenced by coproc_register_read(), coproc_register_write(), coproc_tlbwri(), mips_coproc_new(), and mips_cpu_tlbdump().
#define COP0_XCONTEXT 20 |
Definition at line 146 of file cop0.h.
Referenced by coproc_register_read().
#define COP1_REVISION_DOUBLE 0x20000 /* double precision support */ |
#define COP1_REVISION_SINGLE 0x10000 /* single precision support */ |
#define ENTRYHI_ASID 0xff |
Definition at line 101 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define ENTRYHI_R_MASK 0xc000000000000000ULL |
Definition at line 95 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), and TRANSLATE_ADDRESS().
#define ENTRYHI_R_XKPHYS 0x8000000000000000ULL |
Definition at line 96 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
Definition at line 99 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), and TRANSLATE_ADDRESS().
#define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
Definition at line 98 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), and TRANSLATE_ADDRESS().
#define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */ |
Definition at line 65 of file cop0.h.
Referenced by coproc_register_write(), and mips_coproc_tlb_set_entry().
#define ENTRYLO_C_SHIFT 3 |
Definition at line 66 of file cop0.h.
Referenced by mips_coproc_tlb_set_entry().
#define ENTRYLO_D 0x04 /* Dirty bit */ |
Definition at line 67 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define ENTRYLO_G 0x01 /* Global bit */ |
Definition at line 69 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), and TRANSLATE_ADDRESS().
#define ENTRYLO_PFN_MASK 0x3fffffc0 |
Definition at line 63 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define ENTRYLO_PFN_SHIFT 6 |
Definition at line 64 of file cop0.h.
Referenced by coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define ENTRYLO_V 0x02 /* Valid bit */ |
Definition at line 68 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */ |
Definition at line 187 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define EXCEPTION_ADES 5 /* Address Error Exception (store) */ |
Definition at line 188 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
#define EXCEPTION_CPU 11 /* CoProcessor Unusable */ |
Definition at line 194 of file cop0.h.
Referenced by cop0_availability_check(), coproc_function(), and X().
#define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */ |
Definition at line 190 of file cop0.h.
Referenced by MEMORY_RW().
#define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */ |
Definition at line 189 of file cop0.h.
Referenced by MEMORY_RW().
#define EXCEPTION_MOD 1 /* TLB modification exception */ |
Definition at line 184 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define EXCEPTION_NAMES |
#define EXCEPTION_OV 12 /* Arithmetic Overflow */ |
#define EXCEPTION_RI 10 /* Reserved instruction */ |
#define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */ |
Definition at line 185 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define EXCEPTION_TLBS 3 /* TLB exception (store) */ |
Definition at line 186 of file cop0.h.
Referenced by mips_unaligned_loadstore(), and TRANSLATE_ADDRESS().
#define EXCEPTION_TR 13 /* Trap exception */ |
#define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */ |
#define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
#define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */ |
#define INDEX_MASK 0x3f |
Definition at line 52 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), and mips_cpu_tlbdump().
#define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */ |
Definition at line 51 of file cop0.h.
Referenced by coproc_tlbpr().
#define KSU_KERNEL 0 |
Definition at line 172 of file cop0.h.
Referenced by cop0_availability_check(), and TRANSLATE_ADDRESS().
#define KSU_SUPERVISOR 1 |
Definition at line 173 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define KSU_USER 2 |
Definition at line 174 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define PAGEMASK_MASK 0x01ffe000 |
Definition at line 84 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
Definition at line 86 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define PAGEMASK_SHIFT 13 |
Definition at line 85 of file cop0.h.
Referenced by coproc_register_write(), and TRANSLATE_ADDRESS().
#define PAGEMASK_SHIFT_R4100 11 |
Definition at line 88 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc |
Definition at line 81 of file cop0.h.
Referenced by coproc_register_write().
#define R2K3K_ENTRYHI_ASID_MASK 0xfc0 |
Definition at line 106 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYHI_ASID_SHIFT 6 |
Definition at line 107 of file cop0.h.
Referenced by mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL |
Definition at line 104 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYLO_D 0x400 |
Definition at line 74 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYLO_G 0x100 |
Definition at line 76 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYLO_N 0x800 |
Definition at line 73 of file cop0.h.
Referenced by coproc_register_write(), mips_coproc_tlb_set_entry(), and mips_cpu_tlbdump().
#define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL |
Definition at line 71 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_ENTRYLO_V 0x200 |
Definition at line 75 of file cop0.h.
Referenced by coproc_register_write(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().
#define R2K3K_INDEX_MASK 0x3f00 |
Definition at line 54 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), and mips_cpu_tlbdump().
#define R2K3K_INDEX_SHIFT 8 |
Definition at line 55 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), and mips_cpu_tlbdump().
#define R2K3K_RANDOM_MASK 0x3f00 |
Definition at line 58 of file cop0.h.
Referenced by coproc_tlbwri(), and mips_cpu_tlbdump().
#define R2K3K_RANDOM_SHIFT 8 |
Definition at line 59 of file cop0.h.
Referenced by coproc_tlbwri(), and mips_cpu_tlbdump().
#define R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */ |
#define R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */ |
Definition at line 128 of file cop0.h.
Referenced by mips_coproc_new(), and X().
#define RANDOM_MASK 0x3f |
Definition at line 57 of file cop0.h.
Referenced by coproc_tlbwri(), and mips_cpu_tlbdump().
#define STATUS_BEV 0x00400000 /* boot exception vectors (?) */ |
Definition at line 115 of file cop0.h.
Referenced by mips_coproc_new().
#define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */ |
#define STATUS_CU_SHIFT 28 |
Definition at line 111 of file cop0.h.
Referenced by cop0_availability_check(), and mips_coproc_new().
#define STATUS_ERL 0x04 |
Definition at line 124 of file cop0.h.
Referenced by cop0_availability_check(), coproc_eret(), TRANSLATE_ADDRESS(), and X().
#define STATUS_EXL 0x02 |
Definition at line 125 of file cop0.h.
Referenced by cop0_availability_check(), coproc_eret(), TRANSLATE_ADDRESS(), and X().
#define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */ |
Definition at line 113 of file cop0.h.
Referenced by mips_cpu_new(), and X().
#define STATUS_IM_SHIFT 8 |
Definition at line 118 of file cop0.h.
Referenced by mips_cpu_new().
#define STATUS_KSU_MASK 0x18 |
Definition at line 122 of file cop0.h.
Referenced by cop0_availability_check(), and TRANSLATE_ADDRESS().
#define STATUS_KSU_SHIFT 3 |
Definition at line 123 of file cop0.h.
Referenced by cop0_availability_check(), and TRANSLATE_ADDRESS().
#define STATUS_KX 0x80 |
Definition at line 119 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define STATUS_SX 0x40 |
Definition at line 120 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define STATUS_UX 0x20 |
Definition at line 121 of file cop0.h.
Referenced by TRANSLATE_ADDRESS().
#define TLB_G (1 << 12) |
Definition at line 102 of file cop0.h.
Referenced by coproc_tlbpr(), coproc_tlbwri(), mips_coproc_tlb_set_entry(), mips_cpu_tlbdump(), and TRANSLATE_ADDRESS().