72 #define PPC_CPU_TYPE_DEFS { \ 73 { "PPC405GP", 0x40110000, 32, PPC_NOFP|PPC_NO_DEC, \ 74 13,5,2, 13,5,2, 0,5,1, 0 }, \ 75 { "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\ 76 { "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ 77 { "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ 78 { "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ 79 { "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ 80 { "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ 81 { "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ 82 { "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ 83 { "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ 84 { NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ 92 #define PPC_N_IC_ARGS 3 93 #define PPC_INSTR_ALIGNMENT_SHIFT 2 94 #define PPC_IC_ENTRIES_SHIFT 10 95 #define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT) 96 #define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \ 97 & (PPC_IC_ENTRIES_PER_PAGE-1)) 98 #define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \ 99 + PPC_INSTR_ALIGNMENT_SHIFT)) 107 #define PPC_MAX_VPH_TLB_ENTRIES 128 152 #define PPC_MSR_SF (1ULL << 63) 154 #define PPC_MSR_HV (1ULL << 60) 156 #define PPC_MSR_VEC (1 << 25) 157 #define PPC_MSR_TGPR (1 << 17) 158 #define PPC_MSR_ILE (1 << 16) 159 #define PPC_MSR_EE (1 << 15) 160 #define PPC_MSR_PR (1 << 14) 161 #define PPC_MSR_FP (1 << 13) 162 #define PPC_MSR_ME (1 << 12) 163 #define PPC_MSR_FE0 (1 << 11) 164 #define PPC_MSR_SE (1 << 10) 165 #define PPC_MSR_BE (1 << 9) 166 #define PPC_MSR_FE1 (1 << 8) 167 #define PPC_MSR_IP (1 << 6) 168 #define PPC_MSR_IR (1 << 5) 169 #define PPC_MSR_DR (1 << 4) 170 #define PPC_MSR_PMM (1 << 2) 171 #define PPC_MSR_RI (1 << 1) 172 #define PPC_MSR_LE (1) 175 #define PPC_FPSCR_FX (1 << 31) 176 #define PPC_FPSCR_FEX (1 << 30) 177 #define PPC_FPSCR_VX (1 << 29) 179 #define PPC_FPSCR_VXNAN (1 << 24) 181 #define PPC_FPSCR_FPCC 0x0000f000 182 #define PPC_FPSCR_FPCC_SHIFT 12 183 #define PPC_FPSCR_FL (1 << 15) 184 #define PPC_FPSCR_FG (1 << 14) 185 #define PPC_FPSCR_FE (1 << 13) 186 #define PPC_FPSCR_FU (1 << 12) 189 #define PPC_EXCEPTION_DSI 0x3 190 #define PPC_EXCEPTION_ISI 0x4 191 #define PPC_EXCEPTION_EI 0x5 192 #define PPC_EXCEPTION_FPU 0x8 193 #define PPC_EXCEPTION_DEC 0x9 194 #define PPC_EXCEPTION_SC 0xc 197 #define PPC_XER_SO (1UL << 31) 198 #define PPC_XER_OV (1 << 30) 199 #define PPC_XER_CA (1 << 29) 207 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
209 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
216 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
221 uint64_t *return_addr,
int flags);
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int ppc_run_instr(struct cpu *cpu)
void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int ppc32_run_instr(struct cpu *cpu)
void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define DYNTRANS_ITC(arch)
int ppc_cpu_family_init(struct cpu_family *)
void ppc_exception(struct cpu *cpu, int exception_nr)
void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define VPH_TLBS(arch, ARCH)
void ppc_init_64bit_dummy_tables(struct cpu *cpu)
#define VPH64(arch, ARCH)
#define DYNTRANS_MISC64_DECLARATIONS(arch, ARCH, tlbindextype)
int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define VPH32(arch, ARCH)
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)