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igsfbreg.h
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1 /* GXemul: $Id: igsfbreg.h,v 1.2 2006-08-11 17:43:30 debug Exp $ */
2 /* $NetBSD: igsfbreg.h,v 1.7 2005/12/11 12:21:27 christos Exp $ */
3 
4 /*
5  * Copyright (c) 2002 Valeriy E. Ushakov
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  * notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in the
15  * documentation and/or other materials provided with the distribution.
16  * 3. The name of the author may not be used to endorse or promote products
17  * derived from this software without specific prior written permission
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 /*
32  * Integraphics Systems IGA 168x and CyberPro series.
33  * Only tested on IGA 1682 in Krups JavaStation-NC.
34  */
35 #ifndef _DEV_IC_IGSFBREG_H_
36 #define _DEV_IC_IGSFBREG_H_
37 
38 /*
39  * Magic address decoding for memory space accesses in CyberPro.
40  */
41 #define IGS_MEM_MMIO_SELECT 0x00800000 /* memory mapped i/o */
42 #define IGS_MEM_BE_SELECT 0x00400000 /* endian select */
43 
44 /*
45  * Cursor sprite data in linear memory at IGS_EXT_SPRITE_DATA_{LO,HI}.
46  * 64x64 pixels, 2bpp = 1Kb
47  */
48 #define IGS_CURSOR_DATA_SIZE 1024
49 
50 
51 /*
52  * Starting up the chip.
53  */
54 
55 /* Video Enable/Setup */
56 #define IGS_VDO 0x46e8
57 #define IGS_VDO_ENABLE 0x08
58 #define IGS_VDO_SETUP 0x10
59 
60 /* Video Enable */
61 #define IGS_VSE 0x102
62 #define IGS_VSE_ENABLE 0x01
63 
64 
65 /*
66  * We map only 32 bytes of actual IGS registers at 0x3c0..0x3df.
67  * This macro helps to define register names using their "absolute"
68  * locations - it makes matching defines against docs easier.
69  */
70 #define IGS_REG_BASE 0x3c0
71 #define IGS_REG_SIZE 0x020
72 #define IGS_REG_(x) ((x) - IGS_REG_BASE)
73 
74 
75 /*
76  * Attribute controller. Flip-flop reset by IGS_INPUT_STATUS1 at 0x3da.
77  * We don't bother defining actual registers, we only use them once
78  * during video initialization.
79  */
80 #define IGS_ATTR_IDX IGS_REG_(0x3c0)
81 #define IGS_ATTR_PORT IGS_REG_(0x3c1)
82 
83 
84 /*
85  * Misc output register. We only use the _W register during video
86  * initialization.
87  */
88 #define IGS_MISC_OUTPUT_W IGS_REG_(0x3c2)
89 #define IGS_MISC_OUTPUT_R IGS_REG_(0x3cc)
90 
91 
92 /*
93  * SEQUENCER.
94  */
95 #define IGS_SEQ_IDX IGS_REG_(0x3c4)
96 #define IGS_SEQ_PORT IGS_REG_(0x3c5)
97 
98 #define IGS_SEQ_RESET 0x0
99 #define IGS_SEQ_RESET_ASYNC 0x01
100 #define IGS_SEQ_RESET_SYNC 0x02
101 
102 
103 /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL (3cf/56[2]) == 0 */
104 #define IGS_PEL_MASK IGS_REG_(0x3c6)
105 
106 /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL 3cf/56[2] == 1 */
107 #define IGS_DAC_CMD IGS_REG_(0x3c6)
108 
109 
110 /*
111  * Palette Read/Write: write palette index to the index port.
112  * Read/write R/G/B in three consecutive accesses to data port.
113  * After third access to data the index is autoincremented and you can
114  * proceed with reading/writing data port for the next entry.
115  *
116  * When IGS_EXT_SPRITE_DAC_PEL bit in sprite control is set, these
117  * registers are used to access sprite (i.e. cursor) 2-color palette.
118  * (NB: apparently, in this mode index autoincrement doesn't work).
119  */
120 #define IGS_DAC_PEL_READ_IDX IGS_REG_(0x3c7)
121 #define IGS_DAC_PEL_WRITE_IDX IGS_REG_(0x3c8)
122 #define IGS_DAC_PEL_DATA IGS_REG_(0x3c9)
123 
124 
125 /*
126  * GRAPHICS CONTROLLER registers.
127  */
128 #define IGS_GRFX_IDX IGS_REG_(0x3ce)
129 #define IGS_GRFX_PORT IGS_REG_(0x3cf)
130 
131 
132 /*
133  * EXTENDED registers.
134  */
135 #define IGS_EXT_IDX IGS_REG_(0x3ce)
136 #define IGS_EXT_PORT IGS_REG_(0x3cf)
137 
138 /* [3..0] -> [19..16] of start addr if IGS_EXT_START_ADDR_ON is set */
139 #define IGS_EXT_START_ADDR 0x10
140 #define IGS_EXT_START_ADDR_ON 0x10
141 
142 /* overflow 10th bits for severl crtc registers; interlaced mode select */
143 #define IGS_EXT_VOVFL 0x11
144 #define IGS_EXT_VOVFL_INTERLACED 0x20
145 
146 #define IGS_EXT_IRQ_CTL 0x12
147 #define IGS_EXT_IRQ_ENABLE 0x01
148 
149 
150 
151 /*
152  * Sync Control.
153  * Two-bit combinations for h/v:
154  * 00 - normal, 01 - force 0, 1x - force 1
155  */
156 #define IGS_EXT_SYNC_CTL 0x16
157 #define IGS_EXT_SYNC_H0 0x01
158 #define IGS_EXT_SYNC_H1 0x02
159 #define IGS_EXT_SYNC_V0 0x04
160 #define IGS_EXT_SYNC_V1 0x08
161 
162 /*
163  * For PCI just use normal BAR config.
164  */
165 #define IGS_EXT_BUS_CTL 0x30
166 #define IGS_EXT_BUS_CTL_LINSIZE_SHIFT 0
167 #define IGS_EXT_BUS_CTL_LINSIZE_MASK 0x03
168 #define IGS_EXT_BUS_CTL_LINSIZE(x) \
169  (((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK)
170 
171 /*
172  * COPREN - enable direct access to coprocessor registers
173  * COPASELB - select IGS_COP_BASE_B for COP address
174  */
175 #define IGS_EXT_BIU_MISC_CTL 0x33
176 #define IGS_EXT_BIU_LINEAREN 0x01
177 #define IGS_EXT_BIU_LIN2MEM 0x02
178 #define IGS_EXT_BIU_COPREN 0x04
179 #define IGS_EXT_BIU_COPASELB 0x08
180 #define IGS_EXT_BIU_SEGON 0x10
181 #define IGS_EXT_BIU_SEG2MEM 0x20
182 
183 /*
184  * Linear Address registers
185  * PCI: don't write directly, just use normal PCI configuration
186  * ISA: only bits [23..20] are programmable, the rest MBZ
187  */
188 #define IGS_EXT_LINA_LO 0x34 /* [3..0] -> [23..20] */
189 #define IGS_EXT_LINA_HI 0x35 /* [7..0] -> [31..24] */
190 
191 /* Hardware cursor on-screen location and hot spot */
192 #define IGS_EXT_SPRITE_HSTART_LO 0x50
193 #define IGS_EXT_SPRITE_HSTART_HI 0x51 /* bits [2..0] */
194 #define IGS_EXT_SPRITE_HPRESET 0x52 /* bits [5..0] */
195 
196 #define IGS_EXT_SPRITE_VSTART_LO 0x53
197 #define IGS_EXT_SPRITE_VSTART_HI 0x54 /* bits [2..0] */
198 #define IGS_EXT_SPRITE_VPRESET 0x55 /* bits [5..0] */
199 
200 /* Hardware cursor control */
201 #define IGS_EXT_SPRITE_CTL 0x56
202 #define IGS_EXT_SPRITE_VISIBLE 0x01
203 #define IGS_EXT_SPRITE_64x64 0x02
204 #define IGS_EXT_SPRITE_DAC_PEL 0x04
205  /* bits unrelated to sprite control */
206 #define IGS_EXT_COP_RESET 0x08
207 
208 /* Extended graphics mode */
209 #define IGS_EXT_GRFX_MODE 0x57
210 #define IGS_EXT_GRFX_MODE_EXT 0x01
211 
212 /* Overscan R/G/B registers */
213 #define IGS_EXT_OVERSCAN_RED 0x58
214 #define IGS_EXT_OVERSCAN_GREEN 0x59
215 #define IGS_EXT_OVERSCAN_BLUE 0x5a
216 
217 /* Memory controller */
218 #define IGS_EXT_MEM_CTL0 0x70
219 #define IGS_EXT_MEM_CTL1 0x71
220 #define IGS_EXT_MEM_CTL2 0x72
221 
222 /*
223  * SEQ miscellaneous: number of SL between CCLK - controls visual depth.
224  * These values are for MODE256 == 1, SRMODE = 1 in GRFX/5 mode register.
225  */
226 #define IGS_EXT_SEQ_MISC 0x77
227 #define IGS_EXT_SEQ_IBM_STD 0
228 #define IGS_EXT_SEQ_8BPP 1 /* 256 indexed */
229 #define IGS_EXT_SEQ_16BPP 2 /* HiColor 16bpp, 5-6-5 */
230 #define IGS_EXT_SEQ_32BPP 3 /* TrueColor 32bpp */
231 #define IGS_EXT_SEQ_24BPP 4 /* TrueColor 24bpp */
232 #define IGS_EXT_SEQ_15BPP 6 /* HiColor 16bpp, 5-5-5 */
233 
234 /* Hardware cursor data location in linear memory */
235 #define IGS_EXT_SPRITE_DATA_LO 0x7e
236 #define IGS_EXT_SPRITE_DATA_HI 0x7f /* bits [3..0] */
237 
238 
239 #define IGS_EXT_VCLK0 0xb0 /* mult */
240 #define IGS_EXT_VCLK1 0xb1 /* div */
241 #define IGS_EXT_MCLK0 0xb2 /* mult */
242 #define IGS_EXT_MCLK1 0xb3 /* div */
243 
244 
245 /* ----8<---- end of IGS_EXT registers ----8<---- */
246 
247 
248 
249 /*
250  * CRTC can be at 0x3b4/0x3b5 (mono) or 0x3d4/0x3d5 (color)
251  * controlled by bit 0 in misc output register (r=0x3cc/w=0x3c2).
252  * We forcibly init it to color.
253  */
254 #define IGS_CRTC_IDX IGS_REG_(0x3d4)
255 #define IGS_CRTC_PORT IGS_REG_(0x3d5)
256 
257 /*
258  * Reading this register resets flip-flop at 0x3c0 (attribute
259  * controller) to address register.
260  */
261 #define IGS_INPUT_STATUS1 IGS_REG_(0x3da)
262 
263 
264 
265 /*********************************************************************
266  * IGS Graphic Coprocessor
267  */
268 
269 /*
270  * Coprocessor registers location in I/O space.
271  * Controlled by COPASELB bit in IGS_EXT_BIU_MISC_CTL.
272  */
273 #define IGS_COP_BASE_A 0xaf000 /* COPASELB == 0 */
274 #define IGS_COP_BASE_B 0xbf000 /* COPASELB == 1 */
275 #define IGS_COP_SIZE 0x00400
276 
277 
278 /*
279  * NB: Loaded width values should be 1 less than the actual width!
280  */
281 
282 /*
283  * Coprocessor control.
284  */
285 #define IGS_COP_CTL_REG 0x011
286 #define IGS_COP_CTL_HBRDYZ 0x01
287 #define IGS_COP_CTL_HFEMPTZ 0x02
288 #define IGS_COP_CTL_CMDFF 0x04
289 #define IGS_COP_CTL_SOP 0x08 /* rw */
290 #define IGS_COP_CTL_OPS 0x10
291 #define IGS_COP_CTL_TER 0x20 /* rw */
292 #define IGS_COP_CTL_HBACKZ 0x40
293 #define IGS_COP_CTL_BUSY 0x80
294 
295 
296 /*
297  * Source(s) and destination widths.
298  * 16 bit registers. Only bits [11..0] are used.
299  */
300 #define IGS_COP_SRC_MAP_WIDTH_REG 0x018
301 #define IGS_COP_SRC2_MAP_WIDTH_REG 0x118
302 #define IGS_COP_DST_MAP_WIDTH_REG 0x218
303 
304 
305 /*
306  * Bitmap depth.
307  */
308 #define IGS_COP_MAP_FMT_REG 0x01c
309 #define IGS_COP_MAP_8BPP 0x00
310 #define IGS_COP_MAP_16BPP 0x01
311 #define IGS_COP_MAP_24BPP 0x02
312 #define IGS_COP_MAP_32BPP 0x03
313 
314 
315 /*
316  * Binary operations are defined below. S - source, D - destination,
317  * N - not; a - and, o - or, x - xor.
318  *
319  * For ternary operations, foreground mix function is one of 256
320  * ternary raster operations defined by Win32 API; background mix is
321  * ignored.
322  */
323 #define IGS_COP_FG_MIX_REG 0x048
324 #define IGS_COP_BG_MIX_REG 0x049
325 
326 #define IGS_COP_MIX_0 0x0
327 #define IGS_COP_MIX_SaD 0x1
328 #define IGS_COP_MIX_SaND 0x2
329 #define IGS_COP_MIX_S 0x3
330 #define IGS_COP_MIX_NSaD 0x4
331 #define IGS_COP_MIX_D 0x5
332 #define IGS_COP_MIX_SxD 0x6
333 #define IGS_COP_MIX_SoD 0x7
334 #define IGS_COP_MIX_NSaND 0x8
335 #define IGS_COP_MIX_SxND 0x9
336 #define IGS_COP_MIX_ND 0xa
337 #define IGS_COP_MIX_SoND 0xb
338 #define IGS_COP_MIX_NS 0xc
339 #define IGS_COP_MIX_NSoD 0xd
340 #define IGS_COP_MIX_NSoND 0xe
341 #define IGS_COP_MIX_1 0xf
342 
343 
344 /*
345  * Foreground/background colours (24 bit).
346  * Selected by bits in IGS_COP_PIXEL_OP_3_REG.
347  */
348 #define IGS_COP_FG_REG 0x058
349 #define IGS_COP_BG_REG 0x05C
350 
351 
352 /*
353  * Horizontal/vertical dimensions of pixel blit function.
354  * 16 bit registers. Only [11..0] are used.
355  */
356 #define IGS_COP_WIDTH_REG 0x060
357 #define IGS_COP_HEIGHT_REG 0x062
358 
359 
360 /*
361  * Only bits [21..0] are used.
362  */
363 #define IGS_COP_SRC_BASE_REG 0x070 /* only for 24bpp Src Color Tiling */
364 #define IGS_COP_SRC_START_REG 0x170
365 #define IGS_COP_SRC2_START_REG 0x174
366 #define IGS_COP_DST_START_REG 0x178
367 
368 /*
369  * Destination phase angle for 24bpp.
370  */
371 #define IGS_COP_DST_X_PHASE_REG 0x078
372 #define IGS_COP_DST_X_PHASE_MASK 0x07
373 
374 
375 /*
376  * Pixel operation: Direction and draw mode.
377  * When an octant bit is set, that axis is traversed backwards.
378  */
379 #define IGS_COP_PIXEL_OP_0_REG 0x07c
380 
381 #define IGS_COP_OCTANT_Y_NEG 0x02 /* 0: top down, 1: bottom up */
382 #define IGS_COP_OCTANT_X_NEG 0x04 /* 0: l2r, 1: r2l */
383 
384 #define IGS_COP_DRAW_ALL 0x00
385 #define IGS_COP_DRAW_FIRST_NULL 0x10
386 #define IGS_COP_DRAW_LAST_NULL 0x20
387 
388 
389 /*
390  * Pixel operation: Pattern operation.
391  */
392 #define IGS_COP_PIXEL_OP_1_REG 0x07d
393 
394 #define IGS_COP_PPM_TEXT 0x10
395 #define IGS_COP_PPM_TILE 0x20
396 #define IGS_COP_PPM_LINE 0x30
397 #define IGS_COP_PPM_TRANSPARENT 0x40 /* "or" with one of the above */
398 
399 #define IGS_COP_PPM_FIXED_FG 0x80
400 #define IGS_COP_PPM_SRC_COLOR_TILE 0x90
401 
402 
403 /*
404  * Pixel operation: Host CPU access (host blit) to graphics engine.
405  */
406 #define IGS_COP_PIXEL_OP_2_REG 0x07e
407 #define IGS_COP_HBLTR 0x01 /* enable read from engine */
408 #define IGS_COP_HBLTW 0x02 /* enable write to engine */
409 
410 
411 /*
412  * Pixel operation: Operation function of graphic engine.
413  */
414 #define IGS_COP_PIXEL_OP_3_REG 0x07f
415 #define IGS_COP_OP_STROKE 0x04 /* short stroke */
416 #define IGS_COP_OP_LINE 0x05 /* bresenham line draw */
417 #define IGS_COP_OP_PXBLT 0x08 /* pixel blit */
418 #define IGS_COP_OP_PXBLT_INV 0x09 /* invert pixel blit */
419 #define IGS_COP_OP_PXBLT_3 0x0a /* ternary pixel blit */
420 
421 /* select fg/bg source: 0 - fg/bg color reg, 1 - src1 map */
422 #define IGS_COP_OP_FG_FROM_SRC 0x20
423 #define IGS_COP_OP_BG_FROM_SRC 0x80
424 
425 #endif /* _DEV_IC_IGSFBREG_H_ */

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