87 #define SCC_CHANNEL_A 1 88 #define SCC_CHANNEL_B 0 90 #define SCC_INIT_REG(scc,chan) { \ 92 tmp = (scc)->scc_channel[(chan)].scc_command; \ 93 tmp = (scc)->scc_channel[(chan)].scc_command; \ 96 #define SCC_READ_REG(scc,chan,reg,val) { \ 97 (scc)->scc_channel[(chan)].scc_command = (reg); \ 98 (val) = (scc)->scc_channel[(chan)].scc_command; \ 101 #define SCC_READ_REG_ZERO(scc,chan,val) { \ 102 (val) = (scc)->scc_channel[(chan)].scc_command; \ 105 #define SCC_WRITE_REG(scc,chan,reg,val) { \ 106 (scc)->scc_channel[(chan)].scc_command = (reg); \ 107 (scc)->scc_channel[(chan)].scc_command = (val); \ 110 #define SCC_WRITE_REG_ZERO(scc,chan,val) { \ 111 (scc)->scc_channel[(chan)].scc_command = (val); \ 114 #define SCC_READ_DATA(scc,chan,val) { \ 115 (val) = (scc)->scc_channel[(chan)].scc_data; \ 118 #define SCC_WRITE_DATA(scc,chan,val) { \ 119 (scc)->scc_channel[(chan)].scc_data = (val); \ 152 #define SCC_RR0_BREAK 0x80 153 #define SCC_RR0_ABORT 0x80 154 #define SCC_RR0_TX_UNDERRUN 0x40 155 #define SCC_RR0_CTS 0x20 157 #define SCC_RR0_SYNCH 0x10 158 #define SCC_RR0_DCD 0x08 159 #define SCC_RR0_TX_EMPTY 0x04 160 #define SCC_RR0_ZERO_COUNT 0x02 161 #define SCC_RR0_RX_AVAIL 0x01 163 #define SCC_RR1_EOF 0x80 164 #define SCC_RR1_CRC_ERR 0x40 165 #define SCC_RR1_FRAME_ERR 0x40 166 #define SCC_RR1_RX_OVERRUN 0x20 167 #define SCC_RR1_PARITY_ERR 0x10 168 #define SCC_RR1_RESIDUE0 0x08 169 #define SCC_RR1_RESIDUE1 0x04 170 #define SCC_RR1_RESIDUE2 0x02 171 #define SCC_RR1_ALL_SENT 0x01 176 #define SCC_RR2_STATUS(val) ((val)&0xf) 178 #define SCC_RR2_B_XMIT_DONE 0x0 179 #define SCC_RR2_B_EXT_STATUS 0x2 180 #define SCC_RR2_B_RECV_DONE 0x4 181 #define SCC_RR2_B_RECV_SPECIAL 0x6 182 #define SCC_RR2_A_XMIT_DONE 0x8 183 #define SCC_RR2_A_EXT_STATUS 0xa 184 #define SCC_RR2_A_RECV_DONE 0xc 185 #define SCC_RR2_A_RECV_SPECIAL 0xe 188 #define SCC_RR3_zero 0xc0 189 #define SCC_RR3_RX_IP_A 0x20 190 #define SCC_RR3_TX_IP_A 0x10 191 #define SCC_RR3_EXT_IP_A 0x08 192 #define SCC_RR3_RX_IP_B 0x04 193 #define SCC_RR3_TX_IP_B 0x02 194 #define SCC_RR3_EXT_IP_B 0x01 197 #define SCC_RECV_BUFFER SCC_RR8 198 #define SCC_RECV_FIFO_DEEP 3 200 #define SCC_RR10_1CLKS 0x80 201 #define SCC_RR10_2CLKS 0x40 202 #define SCC_RR10_zero 0x2d 203 #define SCC_RR10_LOOP_SND 0x10 204 #define SCC_RR10_ON_LOOP 0x02 208 #define SCC_GET_TIMING_BASE(scc,chan,val) { \ 210 SCC_READ_REG(scc,chan,SCC_RR12,val);\ 211 SCC_READ_REG(scc,chan,SCC_RR13,tmp);\ 212 (val) = ((val)<<8)|(tmp&0xff);\ 215 #define SCC_RR15_BREAK_IE 0x80 216 #define SCC_RR15_TX_UNDERRUN_IE 0x40 217 #define SCC_RR15_CTS_IE 0x20 218 #define SCC_RR15_SYNCH_IE 0x10 219 #define SCC_RR15_DCD_IE 0x08 220 #define SCC_RR15_zero 0x05 221 #define SCC_RR15_ZERO_COUNT_IE 0x02 227 #define SCC_RESET_TXURUN_LATCH 0xc0 228 #define SCC_RESET_TX_CRC 0x80 229 #define SCC_RESET_RX_CRC 0x40 230 #define SCC_RESET_HIGHEST_IUS 0x38 231 #define SCC_RESET_ERROR 0x30 232 #define SCC_RESET_TX_IP 0x28 233 #define SCC_IE_NEXT_CHAR 0x20 234 #define SCC_SEND_SDLC_ABORT 0x18 235 #define SCC_RESET_EXT_IP 0x10 237 #define SCC_WR1_DMA_ENABLE 0x80 238 #define SCC_WR1_DMA_MODE 0x40 239 #define SCC_WR1_DMA_RECV_DATA 0x20 241 #define SCC_WR1_RXI_SPECIAL_O 0x18 242 #define SCC_WR1_RXI_ALL_CHAR 0x10 243 #define SCC_WR1_RXI_FIRST_CHAR 0x08 244 #define SCC_WR1_RXI_DISABLE 0x00 245 #define SCC_WR1_PARITY_IE 0x04 246 #define SCC_WR1_TX_IE 0x02 247 #define SCC_WR1_EXT_IE 0x01 251 #define SCC_WR3_RX_8_BITS 0xc0 252 #define SCC_WR3_RX_6_BITS 0x80 253 #define SCC_WR3_RX_7_BITS 0x40 254 #define SCC_WR3_RX_5_BITS 0x00 255 #define SCC_WR3_AUTO_ENABLE 0x20 256 #define SCC_WR3_HUNT_MODE 0x10 257 #define SCC_WR3_RX_CRC_ENABLE 0x08 258 #define SCC_WR3_SDLC_SRCH 0x04 259 #define SCC_WR3_INHIBIT_SYNCH 0x02 260 #define SCC_WR3_RX_ENABLE 0x01 263 #define SCC_WR4_CLK_x64 0xc0 264 #define SCC_WR4_CLK_x32 0x80 265 #define SCC_WR4_CLK_x16 0x40 266 #define SCC_WR4_CLK_x1 0x00 267 #define SCC_WR4_EXT_SYNCH_MODE 0x30 268 #define SCC_WR4_SDLC_MODE 0x20 269 #define SCC_WR4_16BIT_SYNCH 0x10 270 #define SCC_WR4_8BIT_SYNCH 0x00 271 #define SCC_WR4_2_STOP 0x0c 272 #define SCC_WR4_1_5_STOP 0x08 273 #define SCC_WR4_1_STOP 0x04 274 #define SCC_WR4_SYNCH_MODE 0x00 275 #define SCC_WR4_EVEN_PARITY 0x02 276 #define SCC_WR4_PARITY_ENABLE 0x01 278 #define SCC_WR5_DTR 0x80 279 #define SCC_WR5_TX_8_BITS 0x60 280 #define SCC_WR5_TX_6_BITS 0x40 281 #define SCC_WR5_TX_7_BITS 0x20 282 #define SCC_WR5_TX_5_BITS 0x00 283 #define SCC_WR5_SEND_BREAK 0x10 284 #define SCC_WR5_TX_ENABLE 0x08 285 #define SCC_WR5_CRC_16 0x04 286 #define SCC_WR5_SDLC 0x00 287 #define SCC_WR5_RTS 0x02 288 #define SCC_WR5_TX_CRC_ENABLE 0x01 292 #define SCC_WR6_BISYNCH_12 0x0f 293 #define SCC_WR6_SDLC_RANGE_MASK 0x0f 294 #define SCC_WR7_SDLC_FLAG 0x7e 297 #define SCC_XMT_BUFFER SCC_WR8 299 #define SCC_WR9_HW_RESET 0xc0 300 #define SCC_WR9_RESET_CHA_A 0x80 301 #define SCC_WR9_RESET_CHA_B 0x40 302 #define SCC_WR9_NON_VECTORED 0x20 303 #define SCC_WR9_STATUS_HIGH 0x10 304 #define SCC_WR9_MASTER_IE 0x08 305 #define SCC_WR9_DLC 0x04 306 #define SCC_WR9_NV 0x02 307 #define SCC_WR9_VIS 0x01 309 #define SCC_WR10_CRC_PRESET 0x80 310 #define SCC_WR10_FM0 0x60 311 #define SCC_WR10_FM1 0x40 312 #define SCC_WR10_NRZI 0x20 313 #define SCC_WR10_NRZ 0x00 314 #define SCC_WR10_ACTIVE_ON_POLL 0x10 315 #define SCC_WR10_MARK_IDLE 0x08 316 #define SCC_WR10_ABORT_ON_URUN 0x04 317 #define SCC_WR10_LOOP_MODE 0x02 318 #define SCC_WR10_6BIT_SYNCH 0x01 319 #define SCC_WR10_8BIT_SYNCH 0x00 321 #define SCC_WR11_RTxC_XTAL 0x80 322 #define SCC_WR11_RCLK_DPLL 0x60 323 #define SCC_WR11_RCLK_BAUDR 0x40 324 #define SCC_WR11_RCLK_TRc_PIN 0x20 325 #define SCC_WR11_RCLK_RTc_PIN 0x00 326 #define SCC_WR11_XTLK_DPLL 0x18 327 #define SCC_WR11_XTLK_BAUDR 0x10 328 #define SCC_WR11_XTLK_TRc_PIN 0x08 329 #define SCC_WR11_XTLK_RTc_PIN 0x00 330 #define SCC_WR11_TRc_OUT 0x04 331 #define SCC_WR11_TRcOUT_DPLL 0x03 332 #define SCC_WR11_TRcOUT_BAUDR 0x02 333 #define SCC_WR11_TRcOUT_XMTCLK 0x01 334 #define SCC_WR11_TRcOUT_XTAL 0x00 337 #define SCC_SET_TIMING_BASE(scc,chan,val) { \ 338 SCC_WRITE_REG(scc,chan,SCC_RR12,val);\ 339 SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\ 343 #define SCC_WR14_NRZI_MODE 0xe0 344 #define SCC_WR14_FM_MODE 0xc0 345 #define SCC_WR14_RTc_SOURCE 0xa0 346 #define SCC_WR14_BAUDR_SOURCE 0x80 347 #define SCC_WR14_DISABLE_DPLL 0x60 348 #define SCC_WR14_RESET_CLKMISS 0x40 349 #define SCC_WR14_SEARCH_MODE 0x20 351 #define SCC_WR14_LOCAL_LOOPB 0x10 352 #define SCC_WR14_AUTO_ECHO 0x08 353 #define SCC_WR14_DTR_REQUEST 0x04 354 #define SCC_WR14_BAUDR_SRC 0x02 355 #define SCC_WR14_BAUDR_ENABLE 0x01 357 #define SCC_WR15_BREAK_IE 0x80 358 #define SCC_WR15_TX_UNDERRUN_IE 0x40 359 #define SCC_WR15_CTS_IE 0x20 360 #define SCC_WR15_SYNCHUNT_IE 0x10 361 #define SCC_WR15_DCD_IE 0x08 362 #define SCC_WR15_zero 0x05 363 #define SCC_WR15_ZERO_COUNT_IE 0x02 366 #define DML_DSR 0000400 367 #define DML_RNG 0000200 368 #define DML_CAR 0000100 369 #define DML_CTS 0000040 370 #define DML_SR 0000020 371 #define DML_ST 0000010 372 #define DML_RTS 0000004 373 #define DML_DTR 0000002 374 #define DML_LE 0000001 381 #define SCCCOMM2_PORT 0x0 382 #define SCCMOUSE_PORT 0x1 383 #define SCCCOMM3_PORT 0x2 384 #define SCCKBD_PORT 0x3
volatile u_char scc_command
struct scc_regmap scc_regmap_t
struct scc_regmap::@18 scc_channel[2]