41 #define DEV_PS2_GS_LENGTH 0x2000 44 #define DEV_PS2_GIF_FAKE_BASE 0x50000000 46 #define N_GS_REGS 0x108 52 #define GS_S_PMODE_REG 0x00 53 #define GS_S_SMODE1_REG 0x01 54 #define GS_S_SMODE2_REG 0x02 55 #define GS_S_SRFSH_REG 0x03 56 #define GS_S_SYNCH1_REG 0x04 57 #define GS_S_SYNCH2_REG 0x05 58 #define GS_S_SYNCV_REG 0x06 59 #define GS_S_DISPFB1_REG 0x07 60 #define GS_S_DISPLAY1_REG 0x08 61 #define GS_S_DISPFB2_REG 0x09 62 #define GS_S_DISPLAY2_REG 0x0a 63 #define GS_S_EXTBUF_REG0 0x0b 64 #define GS_S_EXTDATA_REG 0x0c 65 #define GS_S_EXTWRITE_REG 0x0d 66 #define GS_S_BGCOLOR_REG 0x0e 74 #define GS_S_CSR_REG 0x100 75 #define GS_S_IMR_REG 0x101 76 #define GS_S_BUSDIR_REG 0x104 77 #define GS_S_SIGLBLID_REG 0x108 87 uint64_t idata = 0, odata = 0;
94 regnr = relative_addr / 16;
95 if (relative_addr & 0xf) {
96 debug(
"[ gs unaligned access, addr 0x%x ]\n",
105 switch (relative_addr) {
108 debug(
"[ gs read from addr 0x%x ]\n",
110 odata = d->
reg[regnr];
112 debug(
"[ gs write to addr 0x%x:", (
int)relative_addr);
113 for (i=0; i<len; i++)
116 d->
reg[regnr] = idata;
146 memset(d, 0,
sizeof(
struct gs_data));
148 snprintf(str,
sizeof(str) - 1,
"ps2_gif addr=0x%llx",
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
#define DEV_PS2_GIF_FAKE_BASE
#define DEV_PS2_GS_LENGTH
void * device_add(struct machine *machine, const char *name_and_params)
#define CHECK_ALLOCATION(ptr)
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)