ps2_dmacreg.h File Reference

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ps2_dmacreg.h File Reference

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Macros

#define PS2_PHYS_TO_KSEG1(x)   (x - 0x10008000)
 
#define DMAC_BLOCK_SIZE   16
 
#define DMAC_SLICE_SIZE   128
 
#define DMAC_TRANSFER_QWCMAX   0xffff
 
#define DMAC_REGBASE   PS2_PHYS_TO_KSEG1(0x10008000)
 
#define DMAC_REGSIZE   0x00010000
 
#define D_CTRL_REG   PS2_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
 
#define D_STAT_REG   PS2_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
 
#define D_PCR_REG   PS2_PHYS_TO_KSEG1(0x1000e020) /* priority control */
 
#define D_SQWC_REG   PS2_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
 
#define D_RBOR_REG   PS2_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
 
#define D_RBSR_REG   PS2_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
 
#define D_STADR_REG   PS2_PHYS_TO_KSEG1(0x1000e060) /* stall address */
 
#define D_ENABLER_REG   PS2_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
 
#define D_ENABLEW_REG   PS2_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */
 
#define DMA_CH_VIF0   0 /* to (priority 0) */
 
#define DMA_CH_VIF1   1 /* both */
 
#define DMA_CH_GIF   2 /* to */
 
#define DMA_CH_FROMIPU   3
 
#define DMA_CH_TOIPU   4
 
#define DMA_CH_SIF0   5 /* from */
 
#define DMA_CH_SIF1   6 /* to */
 
#define DMA_CH_SIF2   7 /* both (priority 1) */
 
#define DMA_CH_FROMSPR   8 /* burst channel */
 
#define DMA_CH_TOSPR   9 /* burst channel */
 
#define DMA_CH_VALID(x)   (((x) >= 0) && ((x) <= 9))
 
#define D_CHCR_OFS   0x00
 
#define D_MADR_OFS   0x10
 
#define D_QWC_OFS   0x20
 
#define D_TADR_OFS   0x30
 
#define D_ASR0_OFS   0x40
 
#define D_ASR1_OFS   0x50
 
#define D_SADR_OFS   0x80
 
#define D0_REGBASE   PS2_PHYS_TO_KSEG1(0x10008000)
 
#define D1_REGBASE   PS2_PHYS_TO_KSEG1(0x10009000)
 
#define D2_REGBASE   PS2_PHYS_TO_KSEG1(0x1000a000)
 
#define D3_REGBASE   PS2_PHYS_TO_KSEG1(0x1000b000)
 
#define D4_REGBASE   PS2_PHYS_TO_KSEG1(0x1000b400)
 
#define D5_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c000)
 
#define D6_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c400)
 
#define D7_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c800)
 
#define D8_REGBASE   PS2_PHYS_TO_KSEG1(0x1000d000)
 
#define D9_REGBASE   PS2_PHYS_TO_KSEG1(0x1000d400)
 
#define D_CHCR_REG(base)   (base)
 
#define D_MADR_REG(base)   (base + D_MADR_OFS)
 
#define D_QWC_REG(base)   (base + D_QWC_OFS)
 
#define D_TADR_REG(base)   (base + D_TADR_OFS)
 
#define D_ASR0_REG(base)   (base + D_ASR0_OFS)
 
#define D_ASR1_REG(base)   (base + D_ASR1_OFS)
 
#define D_SADR_REG(base)   (base + D_SADR_OFS)
 
#define D0_CHCR_REG   PS2_PHYS_TO_KSEG1(0x10008000)
 
#define D0_MADR_REG   PS2_PHYS_TO_KSEG1(0x10008010)
 
#define D0_QWC_REG   PS2_PHYS_TO_KSEG1(0x10008020)
 
#define D0_TADR_REG   PS2_PHYS_TO_KSEG1(0x10008030)
 
#define D0_ASR0_REG   PS2_PHYS_TO_KSEG1(0x10008040)
 
#define D0_ASR1_REG   PS2_PHYS_TO_KSEG1(0x10008050)
 
#define D1_CHCR_REG   PS2_PHYS_TO_KSEG1(0x10009000)
 
#define D1_MADR_REG   PS2_PHYS_TO_KSEG1(0x10009010)
 
#define D1_QWC_REG   PS2_PHYS_TO_KSEG1(0x10009020)
 
#define D1_TADR_REG   PS2_PHYS_TO_KSEG1(0x10009030)
 
#define D1_ASR0_REG   PS2_PHYS_TO_KSEG1(0x10009040)
 
#define D1_ASR1_REG   PS2_PHYS_TO_KSEG1(0x10009050)
 
#define D2_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000a000)
 
#define D2_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000a010)
 
#define D2_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000a020)
 
#define D2_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000a030)
 
#define D2_ASR0_REG   PS2_PHYS_TO_KSEG1(0x1000a040)
 
#define D2_ASR1_REG   PS2_PHYS_TO_KSEG1(0x1000a050)
 
#define D3_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000b000)
 
#define D3_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000b010)
 
#define D3_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000b020)
 
#define D4_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000b400)
 
#define D4_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000b410)
 
#define D4_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000b420)
 
#define D4_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000b430)
 
#define D5_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c000)
 
#define D5_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c010)
 
#define D5_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c020)
 
#define D6_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c400)
 
#define D6_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c410)
 
#define D6_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c420)
 
#define D6_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000c430)
 
#define D7_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c800)
 
#define D7_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c810)
 
#define D7_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c820)
 
#define D8_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000d000)
 
#define D8_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000d010)
 
#define D8_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000d020)
 
#define D8_SADR_REG   PS2_PHYS_TO_KSEG1(0x1000d080)
 
#define D9_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000d400)
 
#define D9_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000d410)
 
#define D9_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000d420)
 
#define D9_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000d430)
 
#define D9_SADR_REG   PS2_PHYS_TO_KSEG1(0x1000d480)
 
#define D_CTRL_DMAE   0x00000001 /* all DMA enable/disable */
 
#define D_CTRL_RELE   0x00000002 /* Cycle stealing on/off */
 
#define D_CTRL_MFD_MASK   0x3
 
#define D_CTRL_MFD_SHIFT   2
 
#define D_CTRL_MFD(x)   (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK)
 
#define D_CTRL_MFD_CLR(x)   ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))
 
#define D_CTRL_MFD_SET(x, val)
 
#define D_CTRL_MFD_DISABLE   0
 
#define D_CTRL_MFD_VIF1   2
 
#define D_CTRL_MFD_GIF   3
 
#define D_CTRL_STS_MASK   0x3
 
#define D_CTRL_STS_SHIFT   4
 
#define D_CTRL_STS(x)   (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK)
 
#define D_CTRL_STS_CLR(x)   ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))
 
#define D_CTRL_STS_SET(x, val)
 
#define D_CTRL_STS_NONE   0
 
#define D_CTRL_STS_SIF0   1
 
#define D_CTRL_STS_FROMSPR   2
 
#define D_CTRL_STS_FROMIPU   3
 
#define D_CTRL_STD_MASK   0x3
 
#define D_CTRL_STD_SHIFT   6
 
#define D_CTRL_STD(x)   (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK)
 
#define D_CTRL_STD_CLR(x)   ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))
 
#define D_CTRL_STD_SET(x, val)
 
#define D_CTRL_STD_NONE   0
 
#define D_CTRL_STD_VIF1   1
 
#define D_CTRL_STD_GIF   2
 
#define D_CTRL_STD_SIF1   3
 
#define D_CTRL_RCYC_MASK   0x7
 
#define D_CTRL_RCYC_SHIFT   8
 
#define D_CTRL_RCYC(x)   (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK)
 
#define D_CTRL_RCYC_CLR(x)   ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))
 
#define D_CTRL_RCYC_SET(x, val)
 
#define D_CTRL_RCYC_CYCLE(x)   (8 << (x))
 
#define D_STAT_MEIM   0x40000000
 
#define D_STAT_SIM   0x20000000
 
#define D_STAT_CIM_MASK   0x3ff
 
#define D_STAT_CIM_SHIFT   16
 
#define D_STAT_CIM(x)   (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK)
 
#define D_STAT_CIM_BIT(x)   ((1 << (x)) << D_STAT_CIM_SHIFT)
 
#define D_STAT_CIM9   0x02000000
 
#define D_STAT_CIM8   0x01000000
 
#define D_STAT_CIM7   0x00800000
 
#define D_STAT_CIM6   0x00400000
 
#define D_STAT_CIM5   0x00200000
 
#define D_STAT_CIM4   0x00100000
 
#define D_STAT_CIM3   0x00080000
 
#define D_STAT_CIM2   0x00040000
 
#define D_STAT_CIM1   0x00020000
 
#define D_STAT_CIM0   0x00010000
 
#define D_STAT_BEIS   0x00008000
 
#define D_STAT_MEIS   0x00004000
 
#define D_STAT_SIS   0x00002000
 
#define D_STAT_CIS_MASK   0x3ff
 
#define D_STAT_CIS_SHIFT   0
 
#define D_STAT_CIS_BIT(x)   (1 << (x))
 
#define D_STAT_CIS9   0x00000200
 
#define D_STAT_CIS8   0x00000100
 
#define D_STAT_CIS7   0x00000080
 
#define D_STAT_CIS6   0x00000040
 
#define D_STAT_CIS5   0x00000020
 
#define D_STAT_CIS4   0x00000010
 
#define D_STAT_CIS3   0x00000008
 
#define D_STAT_CIS2   0x00000004
 
#define D_STAT_CIS1   0x00000002
 
#define D_STAT_CIS0   0x00000001
 
#define D_PCR_PCE   0x80000000
 
#define D_PCR_CDE_MASK   0x3ff
 
#define D_PCR_CDE_SHIFT   16
 
#define D_PCR_CDE(x)   (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK)
 
#define D_PCR_CDE_CLR(x)   ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))
 
#define D_PCR_CDE_SET(x, val)
 
#define D_PCR_CDE9   0x02000000
 
#define D_PCR_CDE8   0x01000000
 
#define D_PCR_CDE7   0x00800000
 
#define D_PCR_CDE6   0x00400000
 
#define D_PCR_CDE5   0x00200000
 
#define D_PCR_CDE4   0x00100000
 
#define D_PCR_CDE3   0x00080000
 
#define D_PCR_CDE2   0x00040000
 
#define D_PCR_CDE1   0x00020000
 
#define D_PCR_CDE0   0x00010000
 
#define D_PCR_CPC_MASK   0x3ff
 
#define D_PCR_CPC_SHIFT   0
 
#define D_PCR_CPC(x)   ((x) & D_PCR_CPC_MASK)
 
#define D_PCR_CPC_CLR(x)   ((x) & ~D_PCR_CPC_MASK)
 
#define D_PCR_CPC_SET(x, val)   ((x) | ((val) & D_PCR_CPC_MASK))
 
#define D_PCR_CPC_BIT(x)   (1 << (x))
 
#define D_PCR_CPC9   0x00000200
 
#define D_PCR_CPC8   0x00000100
 
#define D_PCR_CPC7   0x00000080
 
#define D_PCR_CPC6   0x00000040
 
#define D_PCR_CPC5   0x00000020
 
#define D_PCR_CPC4   0x00000010
 
#define D_PCR_CPC3   0x00000008
 
#define D_PCR_CPC2   0x00000004
 
#define D_PCR_CPC1   0x00000002
 
#define D_PCR_CPC0   0x00000001
 
#define D_SQWC_TQWC_MASK   0xff
 
#define D_SQWC_TQWC_SHIFT   16
 
#define D_SQWC_TQWC(x)   (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK)
 
#define D_SQWC_TQWC_CLR(x)   ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))
 
#define D_SQWC_TQWC_SET(x, val)
 
#define D_SQWC_SQWC_MASK   0xff
 
#define D_SQWC_SQWC_SHIFT   0
 
#define D_SQWC_SQWC(x)   (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK)
 
#define D_SQWC_SQWC_CLR(x)   ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))
 
#define D_SQWC_SQWC_SET(x, val)
 
#define D_ENABLE_SUSPEND   0x00010000
 
#define D_CHCR_TAG_MASK   0xff
 
#define D_CHCR_TAG_SHIFT   16
 
#define D_CHCR_TAG(x)   (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK)
 
#define D_CHCR_TAG_CLR(x)   ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))
 
#define D_CHCR_TAG_SET(x, val)
 
#define D_CHCR_STR   0x00000100
 
#define D_CHCR_TIE   0x00000080
 
#define D_CHCR_TTE   0x00000040
 
#define D_CHCR_ASP_MASK   0x3
 
#define D_CHCR_ASP_SHIFT   4
 
#define D_CHCR_ASP(x)   (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK)
 
#define D_CHCR_ASP_CLR(x)   ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))
 
#define D_CHCR_ASP_SET(x, val)
 
#define D_CHCR_ASP_PUSHED_NONE   0
 
#define D_CHCR_ASP_PUSHED_1   1
 
#define D_CHCR_ASP_PUSHED_2   2
 
#define D_CHCR_MOD_MASK   0x3
 
#define D_CHCR_MOD_SHIFT   2
 
#define D_CHCR_MOD(x)   (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK)
 
#define D_CHCR_MOD_CLR(x)   ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))
 
#define D_CHCR_MOD_SET(x, val)
 
#define D_CHCR_MOD_NORMAL   0
 
#define D_CHCR_MOD_CHAIN   1
 
#define D_CHCR_MOD_INTERLEAVE   2
 
#define D_CHCR_DIR   0x00000001
 
#define D_MADR_SPR   0x80000000
 
#define D_TADR_SPR   0x80000000
 
#define D_ASR_SPR   0x80000000
 
#define D_SADR_MASK   0x3fff
 
#define D_SADR_SHIFT   0
 
#define D_SADR(x)   ((uint32_t)(x) & D_SADR_MASK)
 
#define D_QWC_MASK   0xffff
 
#define D_QWC_SHIFT   0
 
#define D_QWC(x)   (((x) >> D_QWC_SHIFT) & D_QWC_MASK)
 
#define D_QWC_CLR(x)   ((x) & ~(D_QWC_MASK << D_QWC_SHIFT))
 
#define D_QWC_SET(x, val)   ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT))
 
#define DMATAG_ADDR_MASK   0xffffffff
 
#define DMATAG_ADDR_SHIFT   32
 
#define DMATAG_ADDR(x)   ((uint32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK))
 
#define DMATAG_ADDR_SET(x, val)   ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT))
 
#define DMATAG_ADDR32_INVALID(x)   ((x) & 0xf) /* 16byte alignment */
 
#define DMATAG_CMD_MASK   0xffffffff
 
#define DMATAG_CMD_SHIFT   0
 
#define DMATAG_CMD(x)   ((uint32_t)((x) & DMATAG_CMD_MASK))
 
#define DMATAG_CMD_IRQ   0x80000000
 
#define DMATAG_CMD_ID_MASK   0x7
 
#define DMATAG_CMD_ID_SHIFT   28
 
#define DMATAG_CMD_ID(x)   (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK)
 
#define DMATAG_CMD_ID_CLR(x)   ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))
 
#define DMATAG_CMD_ID_SET(x, val)
 
#define DMATAG_CMD_SCID_REFE   0
 
#define DMATAG_CMD_SCID_CNT   1
 
#define DMATAG_CMD_SCID_NEXT   2
 
#define DMATAG_CMD_SCID_REF   3
 
#define DMATAG_CMD_SCID_REFS   4 /* VIF1, GIF, SIF1 only */
 
#define DMATAG_CMD_SCID_CALL   5 /* VIF0, VIF1, GIF only */
 
#define DMATAG_CMD_SCID_RET   6 /* VIF0, VIF1, GIF only */
 
#define DMATAG_CMD_SCID_END   7
 
#define DMATAG_CMD_DCID_CNTS   0 /* SIF0, fromSPR only */
 
#define DMATAG_CMD_DCID_CNT   1
 
#define DMATAG_CMD_DCID_END   7
 
#define DMATAG_CMD_PCE_MASK   0x3
 
#define DMATAG_CMD_PCE_SHIFT   26
 
#define DMATAG_CMD_PCE(x)   (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK)
 
#define DMATAG_CMD_PCE_CLR(x)   ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))
 
#define DMATAG_CMD_PCE_SET(x, val)
 
#define DMATAG_CMD_PCE_NONE   0
 
#define DMATAG_CMD_PCE_DISABLE   2
 
#define DMATAG_CMD_PCE_ENABLE   3
 
#define DMATAG_CMD_QWC_MASK   0xffff
 
#define DMATAG_CMD_QWC_SHIFT   0
 
#define DMATAG_CMD_QWC(x)   (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK)
 
#define DMATAG_CMD_QWC_CLR(x)   ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))
 
#define DMATAG_CMD_QWC_SET(x, val)
 

Typedefs

typedef uint64_t dmatag_t
 

Macro Definition Documentation

◆ D0_ASR0_REG

#define D0_ASR0_REG   PS2_PHYS_TO_KSEG1(0x10008040)

Definition at line 114 of file ps2_dmacreg.h.

◆ D0_ASR1_REG

#define D0_ASR1_REG   PS2_PHYS_TO_KSEG1(0x10008050)

Definition at line 115 of file ps2_dmacreg.h.

◆ D0_CHCR_REG

#define D0_CHCR_REG   PS2_PHYS_TO_KSEG1(0x10008000)

Definition at line 110 of file ps2_dmacreg.h.

◆ D0_MADR_REG

#define D0_MADR_REG   PS2_PHYS_TO_KSEG1(0x10008010)

Definition at line 111 of file ps2_dmacreg.h.

◆ D0_QWC_REG

#define D0_QWC_REG   PS2_PHYS_TO_KSEG1(0x10008020)

Definition at line 112 of file ps2_dmacreg.h.

◆ D0_REGBASE

#define D0_REGBASE   PS2_PHYS_TO_KSEG1(0x10008000)

Definition at line 91 of file ps2_dmacreg.h.

◆ D0_TADR_REG

#define D0_TADR_REG   PS2_PHYS_TO_KSEG1(0x10008030)

Definition at line 113 of file ps2_dmacreg.h.

◆ D1_ASR0_REG

#define D1_ASR0_REG   PS2_PHYS_TO_KSEG1(0x10009040)

Definition at line 121 of file ps2_dmacreg.h.

◆ D1_ASR1_REG

#define D1_ASR1_REG   PS2_PHYS_TO_KSEG1(0x10009050)

Definition at line 122 of file ps2_dmacreg.h.

◆ D1_CHCR_REG

#define D1_CHCR_REG   PS2_PHYS_TO_KSEG1(0x10009000)

Definition at line 117 of file ps2_dmacreg.h.

◆ D1_MADR_REG

#define D1_MADR_REG   PS2_PHYS_TO_KSEG1(0x10009010)

Definition at line 118 of file ps2_dmacreg.h.

◆ D1_QWC_REG

#define D1_QWC_REG   PS2_PHYS_TO_KSEG1(0x10009020)

Definition at line 119 of file ps2_dmacreg.h.

◆ D1_REGBASE

#define D1_REGBASE   PS2_PHYS_TO_KSEG1(0x10009000)

Definition at line 92 of file ps2_dmacreg.h.

◆ D1_TADR_REG

#define D1_TADR_REG   PS2_PHYS_TO_KSEG1(0x10009030)

Definition at line 120 of file ps2_dmacreg.h.

◆ D2_ASR0_REG

#define D2_ASR0_REG   PS2_PHYS_TO_KSEG1(0x1000a040)

Definition at line 128 of file ps2_dmacreg.h.

◆ D2_ASR1_REG

#define D2_ASR1_REG   PS2_PHYS_TO_KSEG1(0x1000a050)

Definition at line 129 of file ps2_dmacreg.h.

◆ D2_CHCR_REG

#define D2_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000a000)

Definition at line 124 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ D2_MADR_REG

#define D2_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000a010)

Definition at line 125 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ D2_QWC_REG

#define D2_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000a020)

Definition at line 126 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ D2_REGBASE

#define D2_REGBASE   PS2_PHYS_TO_KSEG1(0x1000a000)

Definition at line 93 of file ps2_dmacreg.h.

◆ D2_TADR_REG

#define D2_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000a030)

Definition at line 127 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ D3_CHCR_REG

#define D3_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000b000)

Definition at line 131 of file ps2_dmacreg.h.

◆ D3_MADR_REG

#define D3_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000b010)

Definition at line 132 of file ps2_dmacreg.h.

◆ D3_QWC_REG

#define D3_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000b020)

Definition at line 133 of file ps2_dmacreg.h.

◆ D3_REGBASE

#define D3_REGBASE   PS2_PHYS_TO_KSEG1(0x1000b000)

Definition at line 94 of file ps2_dmacreg.h.

◆ D4_CHCR_REG

#define D4_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000b400)

Definition at line 135 of file ps2_dmacreg.h.

◆ D4_MADR_REG

#define D4_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000b410)

Definition at line 136 of file ps2_dmacreg.h.

◆ D4_QWC_REG

#define D4_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000b420)

Definition at line 137 of file ps2_dmacreg.h.

◆ D4_REGBASE

#define D4_REGBASE   PS2_PHYS_TO_KSEG1(0x1000b400)

Definition at line 95 of file ps2_dmacreg.h.

◆ D4_TADR_REG

#define D4_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000b430)

Definition at line 138 of file ps2_dmacreg.h.

◆ D5_CHCR_REG

#define D5_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c000)

Definition at line 140 of file ps2_dmacreg.h.

◆ D5_MADR_REG

#define D5_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c010)

Definition at line 141 of file ps2_dmacreg.h.

◆ D5_QWC_REG

#define D5_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c020)

Definition at line 142 of file ps2_dmacreg.h.

◆ D5_REGBASE

#define D5_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c000)

Definition at line 96 of file ps2_dmacreg.h.

◆ D6_CHCR_REG

#define D6_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c400)

Definition at line 144 of file ps2_dmacreg.h.

◆ D6_MADR_REG

#define D6_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c410)

Definition at line 145 of file ps2_dmacreg.h.

◆ D6_QWC_REG

#define D6_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c420)

Definition at line 146 of file ps2_dmacreg.h.

◆ D6_REGBASE

#define D6_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c400)

Definition at line 97 of file ps2_dmacreg.h.

◆ D6_TADR_REG

#define D6_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000c430)

Definition at line 147 of file ps2_dmacreg.h.

◆ D7_CHCR_REG

#define D7_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000c800)

Definition at line 149 of file ps2_dmacreg.h.

◆ D7_MADR_REG

#define D7_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000c810)

Definition at line 150 of file ps2_dmacreg.h.

◆ D7_QWC_REG

#define D7_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000c820)

Definition at line 151 of file ps2_dmacreg.h.

◆ D7_REGBASE

#define D7_REGBASE   PS2_PHYS_TO_KSEG1(0x1000c800)

Definition at line 98 of file ps2_dmacreg.h.

◆ D8_CHCR_REG

#define D8_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000d000)

Definition at line 153 of file ps2_dmacreg.h.

◆ D8_MADR_REG

#define D8_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000d010)

Definition at line 154 of file ps2_dmacreg.h.

◆ D8_QWC_REG

#define D8_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000d020)

Definition at line 155 of file ps2_dmacreg.h.

◆ D8_REGBASE

#define D8_REGBASE   PS2_PHYS_TO_KSEG1(0x1000d000)

Definition at line 99 of file ps2_dmacreg.h.

◆ D8_SADR_REG

#define D8_SADR_REG   PS2_PHYS_TO_KSEG1(0x1000d080)

Definition at line 156 of file ps2_dmacreg.h.

◆ D9_CHCR_REG

#define D9_CHCR_REG   PS2_PHYS_TO_KSEG1(0x1000d400)

Definition at line 158 of file ps2_dmacreg.h.

◆ D9_MADR_REG

#define D9_MADR_REG   PS2_PHYS_TO_KSEG1(0x1000d410)

Definition at line 159 of file ps2_dmacreg.h.

◆ D9_QWC_REG

#define D9_QWC_REG   PS2_PHYS_TO_KSEG1(0x1000d420)

Definition at line 160 of file ps2_dmacreg.h.

◆ D9_REGBASE

#define D9_REGBASE   PS2_PHYS_TO_KSEG1(0x1000d400)

Definition at line 100 of file ps2_dmacreg.h.

◆ D9_SADR_REG

#define D9_SADR_REG   PS2_PHYS_TO_KSEG1(0x1000d480)

Definition at line 162 of file ps2_dmacreg.h.

◆ D9_TADR_REG

#define D9_TADR_REG   PS2_PHYS_TO_KSEG1(0x1000d430)

Definition at line 161 of file ps2_dmacreg.h.

◆ D_ASR0_OFS

#define D_ASR0_OFS   0x40

Definition at line 87 of file ps2_dmacreg.h.

◆ D_ASR0_REG

#define D_ASR0_REG (   base)    (base + D_ASR0_OFS)

Definition at line 106 of file ps2_dmacreg.h.

◆ D_ASR1_OFS

#define D_ASR1_OFS   0x50

Definition at line 88 of file ps2_dmacreg.h.

◆ D_ASR1_REG

#define D_ASR1_REG (   base)    (base + D_ASR1_OFS)

Definition at line 107 of file ps2_dmacreg.h.

◆ D_ASR_SPR

#define D_ASR_SPR   0x80000000

Definition at line 429 of file ps2_dmacreg.h.

◆ D_CHCR_ASP

#define D_CHCR_ASP (   x)    (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK)

Definition at line 384 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_CLR

#define D_CHCR_ASP_CLR (   x)    ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))

Definition at line 386 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_MASK

#define D_CHCR_ASP_MASK   0x3

Definition at line 382 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_PUSHED_1

#define D_CHCR_ASP_PUSHED_1   1

Definition at line 392 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_PUSHED_2

#define D_CHCR_ASP_PUSHED_2   2

Definition at line 393 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_PUSHED_NONE

#define D_CHCR_ASP_PUSHED_NONE   0

Definition at line 391 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_SET

#define D_CHCR_ASP_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CHCR_ASP_SHIFT) & \
#define D_CHCR_ASP_SHIFT
Definition: ps2_dmacreg.h:383
#define D_CHCR_ASP_MASK
Definition: ps2_dmacreg.h:382

Definition at line 388 of file ps2_dmacreg.h.

◆ D_CHCR_ASP_SHIFT

#define D_CHCR_ASP_SHIFT   4

Definition at line 383 of file ps2_dmacreg.h.

◆ D_CHCR_DIR

#define D_CHCR_DIR   0x00000001

Definition at line 411 of file ps2_dmacreg.h.

◆ D_CHCR_MOD

#define D_CHCR_MOD (   x)    (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK)

Definition at line 397 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_CHAIN

#define D_CHCR_MOD_CHAIN   1

Definition at line 405 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_CLR

#define D_CHCR_MOD_CLR (   x)    ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))

Definition at line 399 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_INTERLEAVE

#define D_CHCR_MOD_INTERLEAVE   2

Definition at line 406 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_MASK

#define D_CHCR_MOD_MASK   0x3

Definition at line 395 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_NORMAL

#define D_CHCR_MOD_NORMAL   0

Definition at line 404 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_SET

#define D_CHCR_MOD_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CHCR_MOD_SHIFT) & \
#define D_CHCR_MOD_SHIFT
Definition: ps2_dmacreg.h:396
#define D_CHCR_MOD_MASK
Definition: ps2_dmacreg.h:395

Definition at line 401 of file ps2_dmacreg.h.

◆ D_CHCR_MOD_SHIFT

#define D_CHCR_MOD_SHIFT   2

Definition at line 396 of file ps2_dmacreg.h.

◆ D_CHCR_OFS

#define D_CHCR_OFS   0x00

Definition at line 83 of file ps2_dmacreg.h.

◆ D_CHCR_REG

#define D_CHCR_REG (   base)    (base)

Definition at line 102 of file ps2_dmacreg.h.

◆ D_CHCR_STR

#define D_CHCR_STR   0x00000100

Definition at line 376 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ D_CHCR_TAG

#define D_CHCR_TAG (   x)    (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK)

Definition at line 368 of file ps2_dmacreg.h.

◆ D_CHCR_TAG_CLR

#define D_CHCR_TAG_CLR (   x)    ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))

Definition at line 370 of file ps2_dmacreg.h.

◆ D_CHCR_TAG_MASK

#define D_CHCR_TAG_MASK   0xff

Definition at line 366 of file ps2_dmacreg.h.

◆ D_CHCR_TAG_SET

#define D_CHCR_TAG_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CHCR_TAG_SHIFT) & \
#define D_CHCR_TAG_SHIFT
Definition: ps2_dmacreg.h:367
#define D_CHCR_TAG_MASK
Definition: ps2_dmacreg.h:366

Definition at line 372 of file ps2_dmacreg.h.

◆ D_CHCR_TAG_SHIFT

#define D_CHCR_TAG_SHIFT   16

Definition at line 367 of file ps2_dmacreg.h.

◆ D_CHCR_TIE

#define D_CHCR_TIE   0x00000080

Definition at line 378 of file ps2_dmacreg.h.

◆ D_CHCR_TTE

#define D_CHCR_TTE   0x00000040

Definition at line 380 of file ps2_dmacreg.h.

◆ D_CTRL_DMAE

#define D_CTRL_DMAE   0x00000001 /* all DMA enable/disable */

Definition at line 167 of file ps2_dmacreg.h.

◆ D_CTRL_MFD

#define D_CTRL_MFD (   x)    (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK)

Definition at line 172 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_CLR

#define D_CTRL_MFD_CLR (   x)    ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))

Definition at line 174 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_DISABLE

#define D_CTRL_MFD_DISABLE   0

Definition at line 179 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_GIF

#define D_CTRL_MFD_GIF   3

Definition at line 181 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_MASK

#define D_CTRL_MFD_MASK   0x3

Definition at line 170 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_SET

#define D_CTRL_MFD_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CTRL_MFD_SHIFT) & \
#define D_CTRL_MFD_SHIFT
Definition: ps2_dmacreg.h:171
#define D_CTRL_MFD_MASK
Definition: ps2_dmacreg.h:170

Definition at line 176 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_SHIFT

#define D_CTRL_MFD_SHIFT   2

Definition at line 171 of file ps2_dmacreg.h.

◆ D_CTRL_MFD_VIF1

#define D_CTRL_MFD_VIF1   2

Definition at line 180 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC

#define D_CTRL_RCYC (   x)    (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK)

Definition at line 219 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC_CLR

#define D_CTRL_RCYC_CLR (   x)    ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))

Definition at line 221 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC_CYCLE

#define D_CTRL_RCYC_CYCLE (   x)    (8 << (x))

Definition at line 226 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC_MASK

#define D_CTRL_RCYC_MASK   0x7

Definition at line 217 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC_SET

#define D_CTRL_RCYC_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CTRL_RCYC_SHIFT) & \
#define D_CTRL_RCYC_MASK
Definition: ps2_dmacreg.h:217
#define D_CTRL_RCYC_SHIFT
Definition: ps2_dmacreg.h:218

Definition at line 223 of file ps2_dmacreg.h.

◆ D_CTRL_RCYC_SHIFT

#define D_CTRL_RCYC_SHIFT   8

Definition at line 218 of file ps2_dmacreg.h.

◆ D_CTRL_REG

#define D_CTRL_REG   PS2_PHYS_TO_KSEG1(0x1000e000) /* DMA control */

Definition at line 58 of file ps2_dmacreg.h.

◆ D_CTRL_RELE

#define D_CTRL_RELE   0x00000002 /* Cycle stealing on/off */

Definition at line 168 of file ps2_dmacreg.h.

◆ D_CTRL_STD

#define D_CTRL_STD (   x)    (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK)

Definition at line 201 of file ps2_dmacreg.h.

◆ D_CTRL_STD_CLR

#define D_CTRL_STD_CLR (   x)    ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))

Definition at line 203 of file ps2_dmacreg.h.

◆ D_CTRL_STD_GIF

#define D_CTRL_STD_GIF   2

Definition at line 210 of file ps2_dmacreg.h.

◆ D_CTRL_STD_MASK

#define D_CTRL_STD_MASK   0x3

Definition at line 199 of file ps2_dmacreg.h.

◆ D_CTRL_STD_NONE

#define D_CTRL_STD_NONE   0

Definition at line 208 of file ps2_dmacreg.h.

◆ D_CTRL_STD_SET

#define D_CTRL_STD_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CTRL_STD_SHIFT) & \
#define D_CTRL_STD_MASK
Definition: ps2_dmacreg.h:199
#define D_CTRL_STD_SHIFT
Definition: ps2_dmacreg.h:200

Definition at line 205 of file ps2_dmacreg.h.

◆ D_CTRL_STD_SHIFT

#define D_CTRL_STD_SHIFT   6

Definition at line 200 of file ps2_dmacreg.h.

◆ D_CTRL_STD_SIF1

#define D_CTRL_STD_SIF1   3

Definition at line 211 of file ps2_dmacreg.h.

◆ D_CTRL_STD_VIF1

#define D_CTRL_STD_VIF1   1

Definition at line 209 of file ps2_dmacreg.h.

◆ D_CTRL_STS

#define D_CTRL_STS (   x)    (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK)

Definition at line 186 of file ps2_dmacreg.h.

◆ D_CTRL_STS_CLR

#define D_CTRL_STS_CLR (   x)    ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))

Definition at line 188 of file ps2_dmacreg.h.

◆ D_CTRL_STS_FROMIPU

#define D_CTRL_STS_FROMIPU   3

Definition at line 196 of file ps2_dmacreg.h.

◆ D_CTRL_STS_FROMSPR

#define D_CTRL_STS_FROMSPR   2

Definition at line 195 of file ps2_dmacreg.h.

◆ D_CTRL_STS_MASK

#define D_CTRL_STS_MASK   0x3

Definition at line 184 of file ps2_dmacreg.h.

◆ D_CTRL_STS_NONE

#define D_CTRL_STS_NONE   0

Definition at line 193 of file ps2_dmacreg.h.

◆ D_CTRL_STS_SET

#define D_CTRL_STS_SET (   x,
  val 
)
Value:
((x) | (((val) << D_CTRL_STS_SHIFT) & \
#define D_CTRL_STS_MASK
Definition: ps2_dmacreg.h:184
#define D_CTRL_STS_SHIFT
Definition: ps2_dmacreg.h:185

Definition at line 190 of file ps2_dmacreg.h.

◆ D_CTRL_STS_SHIFT

#define D_CTRL_STS_SHIFT   4

Definition at line 185 of file ps2_dmacreg.h.

◆ D_CTRL_STS_SIF0

#define D_CTRL_STS_SIF0   1

Definition at line 194 of file ps2_dmacreg.h.

◆ D_ENABLE_SUSPEND

#define D_ENABLE_SUSPEND   0x00010000

Definition at line 357 of file ps2_dmacreg.h.

◆ D_ENABLER_REG

#define D_ENABLER_REG   PS2_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */

Definition at line 65 of file ps2_dmacreg.h.

◆ D_ENABLEW_REG

#define D_ENABLEW_REG   PS2_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */

Definition at line 66 of file ps2_dmacreg.h.

◆ D_MADR_OFS

#define D_MADR_OFS   0x10

Definition at line 84 of file ps2_dmacreg.h.

◆ D_MADR_REG

#define D_MADR_REG (   base)    (base + D_MADR_OFS)

Definition at line 103 of file ps2_dmacreg.h.

◆ D_MADR_SPR

#define D_MADR_SPR   0x80000000

Definition at line 417 of file ps2_dmacreg.h.

◆ D_PCR_CDE

#define D_PCR_CDE (   x)    (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK)

Definition at line 280 of file ps2_dmacreg.h.

◆ D_PCR_CDE0

#define D_PCR_CDE0   0x00010000

Definition at line 296 of file ps2_dmacreg.h.

◆ D_PCR_CDE1

#define D_PCR_CDE1   0x00020000

Definition at line 295 of file ps2_dmacreg.h.

◆ D_PCR_CDE2

#define D_PCR_CDE2   0x00040000

Definition at line 294 of file ps2_dmacreg.h.

◆ D_PCR_CDE3

#define D_PCR_CDE3   0x00080000

Definition at line 293 of file ps2_dmacreg.h.

◆ D_PCR_CDE4

#define D_PCR_CDE4   0x00100000

Definition at line 292 of file ps2_dmacreg.h.

◆ D_PCR_CDE5

#define D_PCR_CDE5   0x00200000

Definition at line 291 of file ps2_dmacreg.h.

◆ D_PCR_CDE6

#define D_PCR_CDE6   0x00400000

Definition at line 290 of file ps2_dmacreg.h.

◆ D_PCR_CDE7

#define D_PCR_CDE7   0x00800000

Definition at line 289 of file ps2_dmacreg.h.

◆ D_PCR_CDE8

#define D_PCR_CDE8   0x01000000

Definition at line 288 of file ps2_dmacreg.h.

◆ D_PCR_CDE9

#define D_PCR_CDE9   0x02000000

Definition at line 287 of file ps2_dmacreg.h.

◆ D_PCR_CDE_CLR

#define D_PCR_CDE_CLR (   x)    ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))

Definition at line 282 of file ps2_dmacreg.h.

◆ D_PCR_CDE_MASK

#define D_PCR_CDE_MASK   0x3ff

Definition at line 278 of file ps2_dmacreg.h.

◆ D_PCR_CDE_SET

#define D_PCR_CDE_SET (   x,
  val 
)
Value:
((x) | (((val) << D_PCR_CDE_SHIFT) & \
#define D_PCR_CDE_MASK
Definition: ps2_dmacreg.h:278
#define D_PCR_CDE_SHIFT
Definition: ps2_dmacreg.h:279

Definition at line 284 of file ps2_dmacreg.h.

◆ D_PCR_CDE_SHIFT

#define D_PCR_CDE_SHIFT   16

Definition at line 279 of file ps2_dmacreg.h.

◆ D_PCR_CPC

#define D_PCR_CPC (   x)    ((x) & D_PCR_CPC_MASK)

Definition at line 300 of file ps2_dmacreg.h.

◆ D_PCR_CPC0

#define D_PCR_CPC0   0x00000001

Definition at line 313 of file ps2_dmacreg.h.

◆ D_PCR_CPC1

#define D_PCR_CPC1   0x00000002

Definition at line 312 of file ps2_dmacreg.h.

◆ D_PCR_CPC2

#define D_PCR_CPC2   0x00000004

Definition at line 311 of file ps2_dmacreg.h.

◆ D_PCR_CPC3

#define D_PCR_CPC3   0x00000008

Definition at line 310 of file ps2_dmacreg.h.

◆ D_PCR_CPC4

#define D_PCR_CPC4   0x00000010

Definition at line 309 of file ps2_dmacreg.h.

◆ D_PCR_CPC5

#define D_PCR_CPC5   0x00000020

Definition at line 308 of file ps2_dmacreg.h.

◆ D_PCR_CPC6

#define D_PCR_CPC6   0x00000040

Definition at line 307 of file ps2_dmacreg.h.

◆ D_PCR_CPC7

#define D_PCR_CPC7   0x00000080

Definition at line 306 of file ps2_dmacreg.h.

◆ D_PCR_CPC8

#define D_PCR_CPC8   0x00000100

Definition at line 305 of file ps2_dmacreg.h.

◆ D_PCR_CPC9

#define D_PCR_CPC9   0x00000200

Definition at line 304 of file ps2_dmacreg.h.

◆ D_PCR_CPC_BIT

#define D_PCR_CPC_BIT (   x)    (1 << (x))

Definition at line 303 of file ps2_dmacreg.h.

◆ D_PCR_CPC_CLR

#define D_PCR_CPC_CLR (   x)    ((x) & ~D_PCR_CPC_MASK)

Definition at line 301 of file ps2_dmacreg.h.

◆ D_PCR_CPC_MASK

#define D_PCR_CPC_MASK   0x3ff

Definition at line 298 of file ps2_dmacreg.h.

◆ D_PCR_CPC_SET

#define D_PCR_CPC_SET (   x,
  val 
)    ((x) | ((val) & D_PCR_CPC_MASK))

Definition at line 302 of file ps2_dmacreg.h.

◆ D_PCR_CPC_SHIFT

#define D_PCR_CPC_SHIFT   0

Definition at line 299 of file ps2_dmacreg.h.

◆ D_PCR_PCE

#define D_PCR_PCE   0x80000000

Definition at line 276 of file ps2_dmacreg.h.

◆ D_PCR_REG

#define D_PCR_REG   PS2_PHYS_TO_KSEG1(0x1000e020) /* priority control */

Definition at line 60 of file ps2_dmacreg.h.

◆ D_QWC

#define D_QWC (   x)    (((x) >> D_QWC_SHIFT) & D_QWC_MASK)

Definition at line 445 of file ps2_dmacreg.h.

◆ D_QWC_CLR

#define D_QWC_CLR (   x)    ((x) & ~(D_QWC_MASK << D_QWC_SHIFT))

Definition at line 446 of file ps2_dmacreg.h.

◆ D_QWC_MASK

#define D_QWC_MASK   0xffff

Definition at line 443 of file ps2_dmacreg.h.

◆ D_QWC_OFS

#define D_QWC_OFS   0x20

Definition at line 85 of file ps2_dmacreg.h.

◆ D_QWC_REG

#define D_QWC_REG (   base)    (base + D_QWC_OFS)

Definition at line 104 of file ps2_dmacreg.h.

◆ D_QWC_SET

#define D_QWC_SET (   x,
  val 
)    ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT))

Definition at line 447 of file ps2_dmacreg.h.

◆ D_QWC_SHIFT

#define D_QWC_SHIFT   0

Definition at line 444 of file ps2_dmacreg.h.

◆ D_RBOR_REG

#define D_RBOR_REG   PS2_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */

Definition at line 62 of file ps2_dmacreg.h.

◆ D_RBSR_REG

#define D_RBSR_REG   PS2_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */

Definition at line 63 of file ps2_dmacreg.h.

◆ D_SADR

#define D_SADR (   x)    ((uint32_t)(x) & D_SADR_MASK)

Definition at line 437 of file ps2_dmacreg.h.

◆ D_SADR_MASK

#define D_SADR_MASK   0x3fff

Definition at line 435 of file ps2_dmacreg.h.

◆ D_SADR_OFS

#define D_SADR_OFS   0x80

Definition at line 89 of file ps2_dmacreg.h.

◆ D_SADR_REG

#define D_SADR_REG (   base)    (base + D_SADR_OFS)

Definition at line 108 of file ps2_dmacreg.h.

◆ D_SADR_SHIFT

#define D_SADR_SHIFT   0

Definition at line 436 of file ps2_dmacreg.h.

◆ D_SQWC_REG

#define D_SQWC_REG   PS2_PHYS_TO_KSEG1(0x1000e030) /* interleave size */

Definition at line 61 of file ps2_dmacreg.h.

◆ D_SQWC_SQWC

#define D_SQWC_SQWC (   x)    (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK)

Definition at line 331 of file ps2_dmacreg.h.

◆ D_SQWC_SQWC_CLR

#define D_SQWC_SQWC_CLR (   x)    ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))

Definition at line 333 of file ps2_dmacreg.h.

◆ D_SQWC_SQWC_MASK

#define D_SQWC_SQWC_MASK   0xff

Definition at line 329 of file ps2_dmacreg.h.

◆ D_SQWC_SQWC_SET

#define D_SQWC_SQWC_SET (   x,
  val 
)
Value:
((x) | (((val) << D_SQWC_SQWC_SHIFT) & \
#define D_SQWC_SQWC_MASK
Definition: ps2_dmacreg.h:329
#define D_SQWC_SQWC_SHIFT
Definition: ps2_dmacreg.h:330

Definition at line 335 of file ps2_dmacreg.h.

◆ D_SQWC_SQWC_SHIFT

#define D_SQWC_SQWC_SHIFT   0

Definition at line 330 of file ps2_dmacreg.h.

◆ D_SQWC_TQWC

#define D_SQWC_TQWC (   x)    (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK)

Definition at line 321 of file ps2_dmacreg.h.

◆ D_SQWC_TQWC_CLR

#define D_SQWC_TQWC_CLR (   x)    ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))

Definition at line 323 of file ps2_dmacreg.h.

◆ D_SQWC_TQWC_MASK

#define D_SQWC_TQWC_MASK   0xff

Definition at line 319 of file ps2_dmacreg.h.

◆ D_SQWC_TQWC_SET

#define D_SQWC_TQWC_SET (   x,
  val 
)
Value:
((x) | (((val) << D_SQWC_TQWC_SHIFT) & \
#define D_SQWC_TQWC_SHIFT
Definition: ps2_dmacreg.h:320
#define D_SQWC_TQWC_MASK
Definition: ps2_dmacreg.h:319

Definition at line 325 of file ps2_dmacreg.h.

◆ D_SQWC_TQWC_SHIFT

#define D_SQWC_TQWC_SHIFT   16

Definition at line 320 of file ps2_dmacreg.h.

◆ D_STADR_REG

#define D_STADR_REG   PS2_PHYS_TO_KSEG1(0x1000e060) /* stall address */

Definition at line 64 of file ps2_dmacreg.h.

◆ D_STAT_BEIS

#define D_STAT_BEIS   0x00008000

Definition at line 252 of file ps2_dmacreg.h.

◆ D_STAT_CIM

#define D_STAT_CIM (   x)    (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK)

Definition at line 239 of file ps2_dmacreg.h.

◆ D_STAT_CIM0

#define D_STAT_CIM0   0x00010000

Definition at line 250 of file ps2_dmacreg.h.

◆ D_STAT_CIM1

#define D_STAT_CIM1   0x00020000

Definition at line 249 of file ps2_dmacreg.h.

◆ D_STAT_CIM2

#define D_STAT_CIM2   0x00040000

Definition at line 248 of file ps2_dmacreg.h.

◆ D_STAT_CIM3

#define D_STAT_CIM3   0x00080000

Definition at line 247 of file ps2_dmacreg.h.

◆ D_STAT_CIM4

#define D_STAT_CIM4   0x00100000

Definition at line 246 of file ps2_dmacreg.h.

◆ D_STAT_CIM5

#define D_STAT_CIM5   0x00200000

Definition at line 245 of file ps2_dmacreg.h.

◆ D_STAT_CIM6

#define D_STAT_CIM6   0x00400000

Definition at line 244 of file ps2_dmacreg.h.

◆ D_STAT_CIM7

#define D_STAT_CIM7   0x00800000

Definition at line 243 of file ps2_dmacreg.h.

◆ D_STAT_CIM8

#define D_STAT_CIM8   0x01000000

Definition at line 242 of file ps2_dmacreg.h.

◆ D_STAT_CIM9

#define D_STAT_CIM9   0x02000000

Definition at line 241 of file ps2_dmacreg.h.

◆ D_STAT_CIM_BIT

#define D_STAT_CIM_BIT (   x)    ((1 << (x)) << D_STAT_CIM_SHIFT)

Definition at line 240 of file ps2_dmacreg.h.

◆ D_STAT_CIM_MASK

#define D_STAT_CIM_MASK   0x3ff

Definition at line 237 of file ps2_dmacreg.h.

◆ D_STAT_CIM_SHIFT

#define D_STAT_CIM_SHIFT   16

Definition at line 238 of file ps2_dmacreg.h.

◆ D_STAT_CIS0

#define D_STAT_CIS0   0x00000001

Definition at line 270 of file ps2_dmacreg.h.

◆ D_STAT_CIS1

#define D_STAT_CIS1   0x00000002

Definition at line 269 of file ps2_dmacreg.h.

◆ D_STAT_CIS2

#define D_STAT_CIS2   0x00000004

Definition at line 268 of file ps2_dmacreg.h.

◆ D_STAT_CIS3

#define D_STAT_CIS3   0x00000008

Definition at line 267 of file ps2_dmacreg.h.

◆ D_STAT_CIS4

#define D_STAT_CIS4   0x00000010

Definition at line 266 of file ps2_dmacreg.h.

◆ D_STAT_CIS5

#define D_STAT_CIS5   0x00000020

Definition at line 265 of file ps2_dmacreg.h.

◆ D_STAT_CIS6

#define D_STAT_CIS6   0x00000040

Definition at line 264 of file ps2_dmacreg.h.

◆ D_STAT_CIS7

#define D_STAT_CIS7   0x00000080

Definition at line 263 of file ps2_dmacreg.h.

◆ D_STAT_CIS8

#define D_STAT_CIS8   0x00000100

Definition at line 262 of file ps2_dmacreg.h.

◆ D_STAT_CIS9

#define D_STAT_CIS9   0x00000200

Definition at line 261 of file ps2_dmacreg.h.

◆ D_STAT_CIS_BIT

#define D_STAT_CIS_BIT (   x)    (1 << (x))

Definition at line 260 of file ps2_dmacreg.h.

◆ D_STAT_CIS_MASK

#define D_STAT_CIS_MASK   0x3ff

Definition at line 258 of file ps2_dmacreg.h.

◆ D_STAT_CIS_SHIFT

#define D_STAT_CIS_SHIFT   0

Definition at line 259 of file ps2_dmacreg.h.

◆ D_STAT_MEIM

#define D_STAT_MEIM   0x40000000

Definition at line 233 of file ps2_dmacreg.h.

◆ D_STAT_MEIS

#define D_STAT_MEIS   0x00004000

Definition at line 254 of file ps2_dmacreg.h.

◆ D_STAT_REG

#define D_STAT_REG   PS2_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */

Definition at line 59 of file ps2_dmacreg.h.

◆ D_STAT_SIM

#define D_STAT_SIM   0x20000000

Definition at line 235 of file ps2_dmacreg.h.

◆ D_STAT_SIS

#define D_STAT_SIS   0x00002000

Definition at line 256 of file ps2_dmacreg.h.

◆ D_TADR_OFS

#define D_TADR_OFS   0x30

Definition at line 86 of file ps2_dmacreg.h.

◆ D_TADR_REG

#define D_TADR_REG (   base)    (base + D_TADR_OFS)

Definition at line 105 of file ps2_dmacreg.h.

◆ D_TADR_SPR

#define D_TADR_SPR   0x80000000

Definition at line 423 of file ps2_dmacreg.h.

◆ DMA_CH_FROMIPU

#define DMA_CH_FROMIPU   3

Definition at line 74 of file ps2_dmacreg.h.

◆ DMA_CH_FROMSPR

#define DMA_CH_FROMSPR   8 /* burst channel */

Definition at line 79 of file ps2_dmacreg.h.

◆ DMA_CH_GIF

#define DMA_CH_GIF   2 /* to */

Definition at line 73 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS(), and DEVINIT().

◆ DMA_CH_SIF0

#define DMA_CH_SIF0   5 /* from */

Definition at line 76 of file ps2_dmacreg.h.

◆ DMA_CH_SIF1

#define DMA_CH_SIF1   6 /* to */

Definition at line 77 of file ps2_dmacreg.h.

◆ DMA_CH_SIF2

#define DMA_CH_SIF2   7 /* both (priority 1) */

Definition at line 78 of file ps2_dmacreg.h.

◆ DMA_CH_TOIPU

#define DMA_CH_TOIPU   4

Definition at line 75 of file ps2_dmacreg.h.

◆ DMA_CH_TOSPR

#define DMA_CH_TOSPR   9 /* burst channel */

Definition at line 80 of file ps2_dmacreg.h.

◆ DMA_CH_VALID

#define DMA_CH_VALID (   x)    (((x) >= 0) && ((x) <= 9))

Definition at line 81 of file ps2_dmacreg.h.

◆ DMA_CH_VIF0

#define DMA_CH_VIF0   0 /* to (priority 0) */

Definition at line 71 of file ps2_dmacreg.h.

◆ DMA_CH_VIF1

#define DMA_CH_VIF1   1 /* both */

Definition at line 72 of file ps2_dmacreg.h.

◆ DMAC_BLOCK_SIZE

#define DMAC_BLOCK_SIZE   16

Definition at line 47 of file ps2_dmacreg.h.

◆ DMAC_REGBASE

#define DMAC_REGBASE   PS2_PHYS_TO_KSEG1(0x10008000)

Definition at line 52 of file ps2_dmacreg.h.

◆ DMAC_REGSIZE

#define DMAC_REGSIZE   0x00010000

Definition at line 53 of file ps2_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ DMAC_SLICE_SIZE

#define DMAC_SLICE_SIZE   128

Definition at line 48 of file ps2_dmacreg.h.

◆ DMAC_TRANSFER_QWCMAX

#define DMAC_TRANSFER_QWCMAX   0xffff

Definition at line 49 of file ps2_dmacreg.h.

◆ DMATAG_ADDR

#define DMATAG_ADDR (   x)    ((uint32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK))

Definition at line 463 of file ps2_dmacreg.h.

◆ DMATAG_ADDR32_INVALID

#define DMATAG_ADDR32_INVALID (   x)    ((x) & 0xf) /* 16byte alignment */

Definition at line 468 of file ps2_dmacreg.h.

◆ DMATAG_ADDR_MASK

#define DMATAG_ADDR_MASK   0xffffffff

Definition at line 461 of file ps2_dmacreg.h.

◆ DMATAG_ADDR_SET

#define DMATAG_ADDR_SET (   x,
  val 
)    ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT))

Definition at line 465 of file ps2_dmacreg.h.

◆ DMATAG_ADDR_SHIFT

#define DMATAG_ADDR_SHIFT   32

Definition at line 462 of file ps2_dmacreg.h.

◆ DMATAG_CMD

#define DMATAG_CMD (   x)    ((uint32_t)((x) & DMATAG_CMD_MASK))

Definition at line 475 of file ps2_dmacreg.h.

◆ DMATAG_CMD_DCID_CNT

#define DMATAG_CMD_DCID_CNT   1

Definition at line 499 of file ps2_dmacreg.h.

◆ DMATAG_CMD_DCID_CNTS

#define DMATAG_CMD_DCID_CNTS   0 /* SIF0, fromSPR only */

Definition at line 498 of file ps2_dmacreg.h.

◆ DMATAG_CMD_DCID_END

#define DMATAG_CMD_DCID_END   7

Definition at line 500 of file ps2_dmacreg.h.

◆ DMATAG_CMD_ID

#define DMATAG_CMD_ID (   x)    (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK)

Definition at line 482 of file ps2_dmacreg.h.

◆ DMATAG_CMD_ID_CLR

#define DMATAG_CMD_ID_CLR (   x)    ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))

Definition at line 484 of file ps2_dmacreg.h.

◆ DMATAG_CMD_ID_MASK

#define DMATAG_CMD_ID_MASK   0x7

Definition at line 480 of file ps2_dmacreg.h.

◆ DMATAG_CMD_ID_SET

#define DMATAG_CMD_ID_SET (   x,
  val 
)
Value:
((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \
#define DMATAG_CMD_ID_MASK
Definition: ps2_dmacreg.h:480
#define DMATAG_CMD_ID_SHIFT
Definition: ps2_dmacreg.h:481

Definition at line 486 of file ps2_dmacreg.h.

◆ DMATAG_CMD_ID_SHIFT

#define DMATAG_CMD_ID_SHIFT   28

Definition at line 481 of file ps2_dmacreg.h.

◆ DMATAG_CMD_IRQ

#define DMATAG_CMD_IRQ   0x80000000

Definition at line 478 of file ps2_dmacreg.h.

◆ DMATAG_CMD_MASK

#define DMATAG_CMD_MASK   0xffffffff

Definition at line 473 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE

#define DMATAG_CMD_PCE (   x)    (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK)

Definition at line 504 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_CLR

#define DMATAG_CMD_PCE_CLR (   x)    ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))

Definition at line 506 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_DISABLE

#define DMATAG_CMD_PCE_DISABLE   2

Definition at line 512 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_ENABLE

#define DMATAG_CMD_PCE_ENABLE   3

Definition at line 513 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_MASK

#define DMATAG_CMD_PCE_MASK   0x3

Definition at line 502 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_NONE

#define DMATAG_CMD_PCE_NONE   0

Definition at line 511 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_SET

#define DMATAG_CMD_PCE_SET (   x,
  val 
)
Value:
((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \
#define DMATAG_CMD_PCE_SHIFT
Definition: ps2_dmacreg.h:503
#define DMATAG_CMD_PCE_MASK
Definition: ps2_dmacreg.h:502

Definition at line 508 of file ps2_dmacreg.h.

◆ DMATAG_CMD_PCE_SHIFT

#define DMATAG_CMD_PCE_SHIFT   26

Definition at line 503 of file ps2_dmacreg.h.

◆ DMATAG_CMD_QWC

#define DMATAG_CMD_QWC (   x)    (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK)

Definition at line 517 of file ps2_dmacreg.h.

◆ DMATAG_CMD_QWC_CLR

#define DMATAG_CMD_QWC_CLR (   x)    ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))

Definition at line 519 of file ps2_dmacreg.h.

◆ DMATAG_CMD_QWC_MASK

#define DMATAG_CMD_QWC_MASK   0xffff

Definition at line 515 of file ps2_dmacreg.h.

◆ DMATAG_CMD_QWC_SET

#define DMATAG_CMD_QWC_SET (   x,
  val 
)
Value:
((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \
#define DMATAG_CMD_QWC_MASK
Definition: ps2_dmacreg.h:515
#define DMATAG_CMD_QWC_SHIFT
Definition: ps2_dmacreg.h:516

Definition at line 521 of file ps2_dmacreg.h.

◆ DMATAG_CMD_QWC_SHIFT

#define DMATAG_CMD_QWC_SHIFT   0

Definition at line 516 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_CALL

#define DMATAG_CMD_SCID_CALL   5 /* VIF0, VIF1, GIF only */

Definition at line 494 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_CNT

#define DMATAG_CMD_SCID_CNT   1

Definition at line 490 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_END

#define DMATAG_CMD_SCID_END   7

Definition at line 496 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_NEXT

#define DMATAG_CMD_SCID_NEXT   2

Definition at line 491 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_REF

#define DMATAG_CMD_SCID_REF   3

Definition at line 492 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_REFE

#define DMATAG_CMD_SCID_REFE   0

Definition at line 489 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_REFS

#define DMATAG_CMD_SCID_REFS   4 /* VIF1, GIF, SIF1 only */

Definition at line 493 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SCID_RET

#define DMATAG_CMD_SCID_RET   6 /* VIF0, VIF1, GIF only */

Definition at line 495 of file ps2_dmacreg.h.

◆ DMATAG_CMD_SHIFT

#define DMATAG_CMD_SHIFT   0

Definition at line 474 of file ps2_dmacreg.h.

◆ PS2_PHYS_TO_KSEG1

#define PS2_PHYS_TO_KSEG1 (   x)    (x - 0x10008000)

Definition at line 5 of file ps2_dmacreg.h.

Typedef Documentation

◆ dmatag_t

typedef uint64_t dmatag_t

Definition at line 45 of file ps2_dmacreg.h.


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