mips_cpuregs.h Source File
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Go to the documentation of this file. 56 #ifndef _MIPS_CPUREGS_H_ 57 #define _MIPS_CPUREGS_H_ 61 #if defined(_KERNEL_OPT) 62 #include "opt_cputype.h" 79 #define MIPS_KUSEG_START 0x0 80 #define MIPS_KSEG0_START 0x80000000 81 #define MIPS_KSEG1_START 0xa0000000 82 #define MIPS_KSEG2_START 0xc0000000 83 #define MIPS_MAX_MEM_ADDR 0xbe000000 84 #define MIPS_RESERVED_ADDR 0xbfc80000 86 #define MIPS_PHYS_MASK 0x1fffffff 88 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 89 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) 90 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) 91 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) 94 #define MIPS3_VA_TO_CINDEX(x) \ 95 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) 97 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 98 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 99 #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) 103 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 119 #define MIPS_CR_BR_DELAY 0x80000000 120 #define MIPS_CR_COP_ERR 0x30000000 121 #define MIPS1_CR_EXC_CODE 0x0000003C 122 #define MIPS3_CR_EXC_CODE 0x0000007C 123 #define MIPS_CR_IP 0x0000FF00 124 #define MIPS_CR_EXC_CODE_SHIFT 2 141 #define MIPS_SR_COP_USABILITY 0xf0000000 142 #define MIPS_SR_COP_0_BIT 0x10000000 143 #define MIPS_SR_COP_1_BIT 0x20000000 147 #define MIPS_SR_MX 0x01000000 148 #define MIPS_SR_PX 0x00800000 149 #define MIPS_SR_BEV 0x00400000 150 #define MIPS_SR_TS 0x00200000 154 #define MIPS_SR_INT_IE 0x00000001 176 #define MIPS1_PARITY_ERR 0x00100000 177 #define MIPS1_CACHE_MISS 0x00080000 178 #define MIPS1_PARITY_ZERO 0x00040000 179 #define MIPS1_SWAP_CACHES 0x00020000 180 #define MIPS1_ISOL_CACHES 0x00010000 182 #define MIPS1_SR_KU_OLD 0x00000020 183 #define MIPS1_SR_INT_ENA_OLD 0x00000010 184 #define MIPS1_SR_KU_PREV 0x00000008 185 #define MIPS1_SR_INT_ENA_PREV 0x00000004 186 #define MIPS1_SR_KU_CUR 0x00000002 189 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 190 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 191 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 192 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 193 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 195 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 196 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 197 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 198 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 199 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 205 #define MIPS3_SR_XX 0x80000000 206 #define MIPS3_SR_RP 0x08000000 207 #define MIPS3_SR_FR 0x04000000 208 #define MIPS3_SR_RE 0x02000000 210 #define MIPS3_SR_DIAG_DL 0x01000000 211 #define MIPS3_SR_DIAG_IL 0x00800000 212 #define MIPS3_SR_SR 0x00100000 213 #define MIPS3_SR_EIE 0x00100000 214 #define MIPS3_SR_NMI 0x00080000 215 #define MIPS3_SR_DIAG_CH 0x00040000 216 #define MIPS3_SR_DIAG_CE 0x00020000 217 #define MIPS3_SR_DIAG_PE 0x00010000 218 #define MIPS3_SR_KX 0x00000080 219 #define MIPS3_SR_SX 0x00000040 220 #define MIPS3_SR_UX 0x00000020 221 #define MIPS3_SR_KSU_MASK 0x00000018 222 #define MIPS3_SR_KSU_USER 0x00000010 223 #define MIPS3_SR_KSU_SUPER 0x00000008 224 #define MIPS3_SR_KSU_KERNEL 0x00000000 225 #define MIPS3_SR_ERL 0x00000004 226 #define MIPS3_SR_EXL 0x00000002 229 #undef MIPS_SR_INT_IE 230 #define MIPS_SR_INT_IE 0x00010001 233 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET 234 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 235 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 236 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 237 #define MIPS_SR_KX MIPS3_SR_KX 238 #define MIPS_SR_SX MIPS3_SR_SX 239 #define MIPS_SR_UX MIPS3_SR_UX 241 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 242 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 243 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 244 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 245 #define MIPS_SR_ERL MIPS3_SR_ERL 246 #define MIPS_SR_EXL MIPS3_SR_EXL 253 #define MIPS_INT_MASK 0xff00 254 #define MIPS_INT_MASK_5 0x8000 255 #define MIPS_INT_MASK_4 0x4000 256 #define MIPS_INT_MASK_3 0x2000 257 #define MIPS_INT_MASK_2 0x1000 258 #define MIPS_INT_MASK_1 0x0800 259 #define MIPS_INT_MASK_0 0x0400 260 #define MIPS_HARD_INT_MASK 0xfc00 261 #define MIPS_SOFT_INT_MASK_1 0x0200 262 #define MIPS_SOFT_INT_MASK_0 0x0100 268 #if defined(MIPS3_ENABLE_CLOCK_INTR) 269 #define MIPS3_INT_MASK MIPS_INT_MASK 270 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 272 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 273 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 279 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000 280 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 282 #define MIPS3_CNTXT_PTE_BASE 0xFF800000 283 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 292 #define MIPS3_CONFIG_K0_MASK 0x00000007 299 #define MIPS3_CONFIG_CU 0x00000008 301 #define MIPS3_CONFIG_DB 0x00000010 302 #define MIPS3_CONFIG_IB 0x00000020 303 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 304 (((config) & (bit)) ? 32 : 16) 306 #define MIPS3_CONFIG_DC_MASK 0x000001c0 307 #define MIPS3_CONFIG_DC_SHIFT 6 308 #define MIPS3_CONFIG_IC_MASK 0x00000e00 309 #define MIPS3_CONFIG_IC_SHIFT 9 310 #define MIPS3_CONFIG_C_DEFBASE 0x1000 313 #define MIPS3_CONFIG_CS 0x00001000 314 #define MIPS3_CONFIG_C_4100BASE 0x0400 315 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 316 ((base) << (((config) & (mask)) >> (shift))) 319 #define MIPS3_CONFIG_SE 0x00001000 322 #define MIPS3_CONFIG_EB 0x00002000 325 #define MIPS3_CONFIG_EM 0x00004000 328 #define MIPS3_CONFIG_BE 0x00008000 331 #define MIPS3_CONFIG_SM 0x00010000 334 #define MIPS3_CONFIG_SC 0x00020000 337 #define MIPS3_CONFIG_EW_MASK 0x000c0000 338 #define MIPS3_CONFIG_EW_SHIFT 18 341 #define MIPS3_CONFIG_SW 0x00100000 344 #define MIPS3_CONFIG_SS 0x00200000 347 #define MIPS3_CONFIG_SB_MASK 0x00c00000 348 #define MIPS3_CONFIG_SB_SHIFT 22 349 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 350 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 353 #define MIPS3_CONFIG_EP_MASK 0x0f000000 354 #define MIPS3_CONFIG_EP_SHIFT 24 357 #define MIPS3_CONFIG_EC_MASK 0x70000000 358 #define MIPS3_CONFIG_EC_SHIFT 28 361 #define MIPS3_CONFIG_CM 0x80000000 368 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 369 #define MIPS4_CONFIG_DN_MASK 0x00000018 370 #define MIPS4_CONFIG_CT 0x00000020 371 #define MIPS4_CONFIG_PE 0x00000040 372 #define MIPS4_CONFIG_PM_MASK 0x00000180 373 #define MIPS4_CONFIG_EC_MASK 0x00001e00 374 #define MIPS4_CONFIG_SB 0x00002000 375 #define MIPS4_CONFIG_SK 0x00004000 376 #define MIPS4_CONFIG_BE 0x00008000 377 #define MIPS4_CONFIG_SS_MASK 0x00070000 378 #define MIPS4_CONFIG_SC_MASK 0x00380000 379 #define MIPS4_CONFIG_RESERVED 0x03c00000 380 #define MIPS4_CONFIG_DC_MASK 0x1c000000 381 #define MIPS4_CONFIG_IC_MASK 0xe0000000 383 #define MIPS4_CONFIG_DC_SHIFT 26 384 #define MIPS4_CONFIG_IC_SHIFT 29 386 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 387 ((base) << (((config) & (mask)) >> (shift))) 389 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 390 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 397 #define MIPS_RESET_EXC_VEC 0xBFC00000 398 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000 403 #define MIPS1_GEN_EXC_VEC 0x80000080 408 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 409 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 410 #define MIPS3_GEN_EXC_VEC 0x80000180 415 #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 416 #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 421 #define MIPS3_INTR_EXC_VEC 0x80000200 469 #define MIPS_BIT(n) __CONCAT($,n) 471 #define MIPS_BIT(n) n 473 #define MIPS_COP_0_TLB_INDEX MIPS_BIT(0) 474 #define MIPS_COP_0_TLB_RANDOM MIPS_BIT(1) 477 #define MIPS_COP_0_TLB_CONTEXT MIPS_BIT(4) 479 #define MIPS_COP_0_BAD_VADDR MIPS_BIT(8) 480 #define MIPS_COP_0_TLB_HI MIPS_BIT(10) 481 #define MIPS_COP_0_STATUS MIPS_BIT(12) 482 #define MIPS_COP_0_CAUSE MIPS_BIT(13) 483 #define MIPS_COP_0_EXC_PC MIPS_BIT(14) 484 #define MIPS_COP_0_PRID MIPS_BIT(15) 488 #define MIPS_COP_0_TLB_LOW MIPS_BIT(2) 491 #define MIPS_COP_0_TLB_LO0 MIPS_BIT(2) 492 #define MIPS_COP_0_TLB_LO1 MIPS_BIT(3) 494 #define MIPS_COP_0_TLB_PG_MASK MIPS_BIT(5) 495 #define MIPS_COP_0_TLB_WIRED MIPS_BIT(6) 497 #define MIPS_COP_0_COUNT MIPS_BIT(9) 498 #define MIPS_COP_0_COMPARE MIPS_BIT(11) 500 #define MIPS_COP_0_CONFIG MIPS_BIT(16) 501 #define MIPS_COP_0_LLADDR MIPS_BIT(17) 502 #define MIPS_COP_0_WATCH_LO MIPS_BIT(18) 503 #define MIPS_COP_0_WATCH_HI MIPS_BIT(19) 504 #define MIPS_COP_0_TLB_XCONTEXT MIPS_BIT(20) 505 #define MIPS_COP_0_ECC MIPS_BIT(26) 506 #define MIPS_COP_0_CACHE_ERR MIPS_BIT(27) 507 #define MIPS_COP_0_TAG_LO MIPS_BIT(28) 508 #define MIPS_COP_0_TAG_HI MIPS_BIT(29) 509 #define MIPS_COP_0_ERROR_PC MIPS_BIT(30) 512 #define MIPS_COP_0_DEBUG MIPS_BIT(23) 513 #define MIPS_COP_0_DEPC MIPS_BIT(24) 514 #define MIPS_COP_0_PERFCNT MIPS_BIT(25) 515 #define MIPS_COP_0_DATA_LO MIPS_BIT(28) 516 #define MIPS_COP_0_DATA_HI MIPS_BIT(29) 517 #define MIPS_COP_0_DESAVE MIPS_BIT(31) 522 #define MIPS_BREAK_INSTR 0x0000000d 523 #define MIPS_BREAK_VAL_MASK 0x03ff0000 524 #define MIPS_BREAK_VAL_SHIFT 16 525 #define MIPS_BREAK_KDB_VAL 512 526 #define MIPS_BREAK_SSTEP_VAL 513 527 #define MIPS_BREAK_BRKPT_VAL 514 528 #define MIPS_BREAK_SOVER_VAL 515 529 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 530 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 531 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 532 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 533 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 534 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 535 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 536 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 541 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 542 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 543 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) 548 #define MIPS_FPU_ID $0 549 #define MIPS_FPU_CSR $31 554 #define MIPS_FPU_ROUNDING_BITS 0x00000003 555 #define MIPS_FPU_ROUND_RN 0x00000000 556 #define MIPS_FPU_ROUND_RZ 0x00000001 557 #define MIPS_FPU_ROUND_RP 0x00000002 558 #define MIPS_FPU_ROUND_RM 0x00000003 559 #define MIPS_FPU_STICKY_BITS 0x0000007c 560 #define MIPS_FPU_STICKY_INEXACT 0x00000004 561 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 562 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 563 #define MIPS_FPU_STICKY_DIV0 0x00000020 564 #define MIPS_FPU_STICKY_INVALID 0x00000040 565 #define MIPS_FPU_ENABLE_BITS 0x00000f80 566 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 567 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 568 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 569 #define MIPS_FPU_ENABLE_DIV0 0x00000400 570 #define MIPS_FPU_ENABLE_INVALID 0x00000800 571 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 572 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 573 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 574 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 575 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 576 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 577 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 578 #define MIPS_FPU_COND_BIT 0x00800000 579 #define MIPS_FPU_FLUSH_BIT 0x01000000 580 #define MIPS1_FPC_MBZ_BITS 0xff7c0000 581 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000 587 #define MIPS_OPCODE_SHIFT 26 588 #define MIPS_OPCODE_C1 0x11 594 #define MIPS1_TLB_PFN 0xfffff000 595 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 596 #define MIPS1_TLB_DIRTY_BIT 0x00000400 597 #define MIPS1_TLB_VALID_BIT 0x00000200 598 #define MIPS1_TLB_GLOBAL_BIT 0x00000100 600 #define MIPS3_TLB_PFN 0x3fffffc0 601 #define MIPS3_TLB_ATTR_MASK 0x00000038 602 #define MIPS3_TLB_ATTR_SHIFT 3 603 #define MIPS3_TLB_DIRTY_BIT 0x00000004 604 #define MIPS3_TLB_VALID_BIT 0x00000002 605 #define MIPS3_TLB_GLOBAL_BIT 0x00000001 607 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12 608 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6 609 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 610 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 611 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 612 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 625 #define MIPS3_TLB_ATTR_WT 0 626 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 627 #define MIPS3_TLB_ATTR_UNCACHED 2 628 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 629 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 630 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 631 #define MIPS3_TLB_ATTR_WB_UPDATE 6 632 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 638 #define MIPS1_TLB_VPN 0xfffff000 639 #define MIPS1_TLB_PID 0x00000fc0 640 #define MIPS1_TLB_PID_SHIFT 6 642 #define MIPS3_TLB_VPN2 0xffffe000 643 #define MIPS3_TLB_ASID 0x000000ff 645 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 646 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 647 #define MIPS3_TLB_PID MIPS3_TLB_ASID 648 #define MIPS_TLB_VIRT_PAGE_SHIFT 12 653 #define MIPS1_TLB_INDEX_SHIFT 8 658 #define MIPS1_TLB_FIRST_RAND_ENTRY 8 659 #define MIPS3_TLB_WIRED_UPAGES 1 664 #define MIPS1_TLB_NUM_PIDS 64 665 #define MIPS3_TLB_NUM_ASIDS 256 673 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 675 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 676 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 679 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 681 #define MIPS_TLB_PID_SHIFT 0 682 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 686 #if !defined(MIPS_TLB_PID_SHIFT) 687 #define MIPS_TLB_PID_SHIFT \ 688 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 690 #define MIPS_TLB_NUM_PIDS \ 691 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 697 #define MIPS_R2000 0x01 698 #define MIPS_R3000 0x02 699 #define MIPS_R6000 0x03 700 #define MIPS_R4000 0x04 701 #define MIPS_R3LSI 0x05 702 #define MIPS_R6000A 0x06 703 #define MIPS_R3IDT 0x07 704 #define MIPS_R10000 0x09 705 #define MIPS_R4200 0x0a 706 #define MIPS_R4300 0x0b 707 #define MIPS_R4100 0x0c 708 #define MIPS_R12000 0x0e 709 #define MIPS_R14000 0x0f 710 #define MIPS_R8000 0x10 711 #define MIPS_RC32300 0x18 712 #define MIPS_R4600 0x20 713 #define MIPS_R4700 0x21 714 #define MIPS_R3SONY 0x21 715 #define MIPS_R4650 0x22 716 #define MIPS_TX3900 0x22 717 #define MIPS_R5000 0x23 718 #define MIPS_R3NKK 0x23 719 #define MIPS_RC32364 0x26 720 #define MIPS_RM7000 0x27 721 #define MIPS_RM5200 0x28 722 #define MIPS_TX4900 0x2d 723 #define MIPS_R5900 0x2e 724 #define MIPS_RC64470 0x30 725 #define MIPS_TX7900 0x38 726 #define MIPS_R5400 0x54 727 #define MIPS_R5500 0x55 734 #define MIPS_REV_R3000 0x20 735 #define MIPS_REV_R3000A 0x30 738 #define MIPS_REV_TX3912 0x10 739 #define MIPS_REV_TX3922 0x30 740 #define MIPS_REV_TX3927 0x40 743 #define MIPS_REV_R4000_A 0x00 744 #define MIPS_REV_R4000_B 0x22 745 #define MIPS_REV_R4000_C 0x30 746 #define MIPS_REV_R4400_A 0x40 747 #define MIPS_REV_R4400_B 0x50 748 #define MIPS_REV_R4400_C 0x60 751 #define MIPS_REV_TX4927 0x22 756 #define MIPS_4Kc 0x80 757 #define MIPS_5Kc 0x81 758 #define MIPS_20Kc 0x82 759 #define MIPS_4Kmp 0x83 760 #define MIPS_4KEc 0x84 761 #define MIPS_4KEmp 0x85 762 #define MIPS_4KSc 0x86 763 #define MIPS_M4K 0x87 764 #define MIPS_25Kf 0x88 765 #define MIPS_5KE 0x89 766 #define MIPS_4KEc_R2 0x90 767 #define MIPS_4KEmp_R2 0x91 768 #define MIPS_4KSd 0x92 769 #define MIPS_24K 0x93 770 #define MIPS_34K 0x95 771 #define MIPS_24KE 0x96 772 #define MIPS_74K 0x97 779 #define MIPS_AU_REV1 0x01 780 #define MIPS_AU_REV2 0x02 782 #define MIPS_AU1000 0x00 783 #define MIPS_AU1500 0x01 784 #define MIPS_AU1100 0x02 785 #define MIPS_AU1550 0x03 790 #define MIPS_SB1 0x01 795 #define MIPS_SR7100 0x04 800 #define MIPS_SOFT 0x00 801 #define MIPS_R2360 0x01 802 #define MIPS_R2010 0x02 803 #define MIPS_R3010 0x03 804 #define MIPS_R6010 0x04 805 #define MIPS_R4010 0x05 806 #define MIPS_R31LSI 0x06 807 #define MIPS_R3TOSH 0x22 809 #ifdef ENABLE_MIPS_TX3900 810 #include <mips/r3900regs.h> 813 #include <mips/r5900regs.h> 816 #include <mips/sb1regs.h>
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