dc21285reg.h Source File
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Go to the documentation of this file. 47 #define VENDOR_ID 0x00 48 #define DC21285_VENDOR_ID 0x1011 49 #define DEVICE_ID 0x02 50 #define DC21285_DEVICE_ID 0x1065 56 #define OUTBOUND_INT_STATUS 0x030 57 #define OUTBOUND_INT_MASK 0x034 58 #define I2O_INBOUND_FIFO 0x040 59 #define I2O_OUTBOUND_FIFO 0x044 63 #define MAILBOX_0 0x050 64 #define MAILBOX_1 0x054 65 #define MAILBOX_2 0x058 66 #define MAILBOX_3 0x05C 68 #define DOORBELL 0x060 69 #define DOORBELL_SETUP 0x064 70 #define ROM_WRITE_BYTE_ADDRESS 0x068 74 #define DMA_CHAN_1_BYTE_COUNT 0x80 75 #define DMA_CHAN_1_PCI_ADDR 0x84 76 #define DMA_CHAN_1_SDRAM_ADDR 0x88 77 #define DMA_CHAN_1_DESCRIPT 0x8C 78 #define DMA_CHAN_1_CONTROL 0x90 79 #define DMA_CHAN_2_BYTE_COUNT 0xA0 80 #define DMA_CHAN_2_PCI_ADDR 0xA4 81 #define DMA_CHAN_2_SDRAM_ADDR 0xA8 82 #define DMA_CHAN_2_DESCRIPTOR 0xAC 83 #define DMA_CHAN_2_CONTROL 0xB0 87 #define DMA_BYTE_COUNT 0 88 #define DMA_PCI_ADDRESS 4 89 #define DMA_SDRAM_ADDRESS 8 90 #define DMA_NEXT_DESCRIPTOR 12 94 #define DMA_INTERBURST_SHIFT 24 95 #define DMA_PCI_TO_SDRAM 0 96 #define DMA_SDRAM_TO_PCI (1 << 30) 97 #define DMA_END_CHAIN (1 << 31) 101 #define DMA_ENABLE (1 << 0) 102 #define DMA_TRANSFER_DONE (1 << 2) 103 #define DMA_ERROR (1 << 3) 104 #define DMA_REGISTOR_DESCRIPTOR (1 << 4) 105 #define DMA_PCI_MEM_READ (0 << 5) 106 #define DMA_PCI_MEM_READ_LINE (1 << 5) 107 #define DMA_PCI_MEM_READ_MULTI1 (2 << 5) 108 #define DMA_PCI_MEM_READ_MULTI2 (3 << 5) 109 #define DMA_CHAIN_DONE (1 << 7) 110 #define DMA_INTERBURST_4 (0 << 8) 111 #define DMA_INTERBURST_8 (1 << 8) 112 #define DMA_INTERBURST_16 (2 << 8) 113 #define DMA_INTERBURST_32 (3 << 8) 114 #define DMA_PCI_LENGTH_8 0 115 #define DMA_PCI_LENGTH_16 (1 << 15) 116 #define DMA_SDRAM_LENGTH_1 (0 << 16) 117 #define DMA_SDRAM_LENGTH_2 (1 << 16) 118 #define DMA_SDRAM_LENGTH_4 (2 << 16) 119 #define DMA_SDRAM_LENGTH_8 (3 << 16) 120 #define DMA_SDRAM_LENGTH_16 (4 << 16) 124 #define CSR_BA_MASK 0x0F8 125 #define CSR_MASK_128B 0x00000000 126 #define CSR_MASK_512KB 0x00040000 127 #define CSR_MASK_1MB 0x000C0000 128 #define CSR_MASK_2MB 0x001C0000 129 #define CSR_MASK_4MB 0x003C0000 130 #define CSR_MASK_8MB 0x007C0000 131 #define CSR_MASK_16MB 0x00FC0000 132 #define CSR_MASK_32MB 0x01FC0000 133 #define CSR_MASK_64MB 0x03FC0000 134 #define CSR_MASK_128MB 0x07FC0000 135 #define CSR_MASK_256MB 0x0FFC0000 136 #define CSR_BA_OFFSET 0x0FC 140 #define SDRAM_BA_MASK 0x100 141 #define SDRAM_MASK_256KB 0x00000000 142 #define SDRAM_MASK_512KB 0x00040000 143 #define SDRAM_MASK_1MB 0x000C0000 144 #define SDRAM_MASK_2MB 0x001C0000 145 #define SDRAM_MASK_4MB 0x003C0000 146 #define SDRAM_MASK_8MB 0x007C0000 147 #define SDRAM_MASK_16MB 0x00FC0000 148 #define SDRAM_MASK_32MB 0x01FC0000 149 #define SDRAM_MASK_64MB 0x03FC0000 150 #define SDRAM_MASK_128MB 0x07FC0000 151 #define SDRAM_MASK_256MB 0x0FFC0000 152 #define SDRAM_WINDOW_DISABLE (1 << 31) 153 #define SDRAM_BA_OFFSET 0x104 157 #define EXPANSION_ROM_BA_MASK 0x108 158 #define ROM_MASK_1MB 0x00000000 159 #define ROM_MASK_2MB 0x00100000 160 #define ROM_MASK_4MB 0x00300000 161 #define ROM_MASK_8MB 0x00700000 162 #define ROM_MASK_16MB 0x00F00000 163 #define ROM_WINDOW_DISABLE (1 << 31) 167 #define SDRAM_TIMING 0x10C 168 #define SDRAM_ARRAY_SIZE_0 0x0 169 #define SDRAM_ARRAY_SIZE_1MB 0x1 170 #define SDRAM_ARRAY_SIZE_2MB 0x2 171 #define SDRAM_ARRAY_SIZE_4MB 0x3 172 #define SDRAM_ARRAY_SIZE_8MB 0x4 173 #define SDRAM_ARRAY_SIZE_16MB 0x5 174 #define SDRAM_ARRAY_SIZE_32MB 0x6 175 #define SDRAM_ARRAY_SIZE_64MB 0x7 176 #define SDRAM_2_BANKS 0 177 #define SDRAM_4_BANKS (1 << 3) 178 #define SDRAM_ADDRESS_MUX_SHIFT 4 179 #define SDRAM_ARRAY_BASE_SHIFT 20 180 #define SDRAM_ADDRESS_SIZE_0 0x110 181 #define SDRAM_ADDRESS_SIZE_1 0x114 182 #define SDRAM_ADDRESS_SIZE_2 0x118 183 #define SDRAM_ADDRESS_SIZE_3 0x11C 187 #define I2O_INBOUND_FREE_HEAD 0x120 188 #define I2O_INBOUND_POST_TAIL 0x124 189 #define I2O_OUTBOUND_POST_HEAD 0x128 190 #define I2O_OUTBOUND_FREE_TAIL 0x12c 191 #define I2O_INBOUND_FREE_COUNT 0x130 192 #define I2O_OUTBOUND_POST_COUNT 0x134 193 #define I2O_INBOUND_POST_COUNT 0x138 197 #define SA_CONTROL 0x13C 198 #define INITIALIZE_COMPLETE (1 << 0) 199 #define ASSERT_SERR (1 << 1) 200 #define RECEIVED_SERR (1 << 3) 201 #define SA_SDRAM_PARITY_ERROR (1 << 4) 202 #define PCI_SDRAM_PARITY_ERROR (1 << 5) 203 #define DMA_SDRAM_PARITY_ERROR (1 << 6) 204 #define DISCARD_TIMER_EXPIRED (1 << 8) 205 #define PCI_NOT_RESET (1 << 9) 206 #define WATCHDOG_ENABLE (1 << 13) 207 #define I2O_SIZE_256 (0 << 10) 208 #define I2O_SIZE_512 (1 << 10) 209 #define I2O_SIZE_1024 (2 << 10) 210 #define I2O_SIZE_2048 (3 << 10) 211 #define I2O_SIZE_4096 (4 << 10) 212 #define I2O_SIZE_8192 (5 << 10) 213 #define I2O_SIZE_16384 (6 << 10) 214 #define I2O_SIZE_32768 (7 << 10) 215 #define ROM_WIDTH_8 (3 << 14) 216 #define ROM_WIDTH_16 (1 << 14) 217 #define ROM_WIDTH_32 (2 << 14) 218 #define ROM_ACCESS_TIME_SHIFT 16 219 #define ROM_BURST_TIME_SHIFT 20 220 #define ROM_TRISTATE_TIME_SHIFT 24 221 #define XCS_DIRECTION_SHIFT 28 222 #define PCI_CENTRAL_FUNCTION (1 << 31) 224 #define PCI_ADDRESS_EXTENSION 0x140 225 #define PREFETCHABLE_MEM_RANGE 0x144 229 #define XBUS_CYCLE_ARBITER 0x148 230 #define XBUS_CYCLE_0_SHIFT 0 231 #define XBUS_CYCLE_1_SHIFT 3 232 #define XBUS_CYCLE_2_SHIFT 6 233 #define XBUS_CYCLE_3_SHIFT 9 234 #define XBUS_CYCLE_STROBE_SHIFT 12 235 #define XBUS_PCI_ARBITER (1 << 23) 236 #define XBUS_INT_IN_L0_LOW 0 237 #define XBUS_INT_IN_L0_HIGH (1 << 24) 238 #define XBUS_INT_IN_L1_LOW 0 239 #define XBUS_INT_IN_L1_HIGH (1 << 25) 240 #define XBUS_INT_IN_L2_LOW 0 241 #define XBUS_INT_IN_L2_HIGH (1 << 26) 242 #define XBUS_INT_IN_L3_LOW 0 243 #define XBUS_INT_IN_L3_HIGH (1 << 27) 244 #define XBUS_INT_XCS0_LOW 0 245 #define XBUS_INT_XCS0_HIGH (1 << 28) 246 #define XBUS_INT_XCS1_LOW 0 247 #define XBUS_INT_XCS1_HIGH (1 << 29) 248 #define XBUS_INT_XCS2_LOW 0 249 #define XBUS_INT_XCS2_HIGH (1 << 30) 250 #define XBUS_PCI_INT_REQUEST (1 << 31) 252 #define XBUS_IO_STROBE_MASK 0x14C 253 #define XBUS_IO_STROBE_0_SHIFT 0 254 #define XBUS_IO_STROBE_2_SHIFT 8 255 #define XBUS_IO_STROBE_3_SHIFT 16 256 #define XBUS_IO_STROBE_4_SHIFT 24 258 #define DOORBELL_PCI_MASK 0x150 259 #define DOORBELL_SA_MASK 0x154 263 #define UART_DATA 0x160 264 #define UART_RX_STAT 0x164 265 #define UART_PARITY_ERROR 0x01 266 #define UART_FRAME_ERROR 0x02 267 #define UART_OVERRUN_ERROR 0x04 268 #define UART_RX_ERROR (UART_PARITY_ERROR | UART_FRAME_ERROR \ 269 | UART_OVERRUN_ERROR) 270 #define UART_H_UBRLCR 0x168 271 #define UART_BREAK 0x01 272 #define UART_PARITY_ENABLE 0x02 273 #define UART_ODD_PARITY 0x00 274 #define UART_EVEN_PARITY 0x04 275 #define UART_STOP_BITS_1 0x00 276 #define UART_STOP_BITS_2 0x08 277 #define UART_ENABLE_FIFO 0x10 278 #define UART_DATA_BITS_5 0x00 279 #define UART_DATA_BITS_6 0x20 280 #define UART_DATA_BITS_7 0x40 281 #define UART_DATA_BITS_8 0x60 282 #define UART_M_UBRLCR 0x16C 283 #define UART_L_UBRLCR 0x170 284 #define UART_BRD(fclk, x) (((fclk) / 4 / 16 / x) - 1) 286 #define UART_CONTROL 0x174 287 #define UART_ENABLE 0x01 288 #define UART_SIR_ENABLE 0x02 289 #define UART_IRDA_ENABLE 0x04 290 #define UART_FLAGS 0x178 291 #define UART_TX_BUSY 0x08 292 #define UART_RX_FULL 0x10 293 #define UART_TX_EMPTY 0x20 297 #define IRQ_RESERVED0 0x00 298 #define IRQ_SOFTINT 0x01 299 #define IRQ_SERIAL_RX 0x02 300 #define IRQ_SERIAL_TX 0x03 301 #define IRQ_TIMER_1 0x04 302 #define IRQ_TIMER_2 0x05 303 #define IRQ_TIMER_3 0x06 304 #define IRQ_TIMER_4 0x07 305 #define IRQ_IN_L0 0x08 306 #define IRQ_IN_L1 0x09 307 #define IRQ_IN_L2 0x0A 308 #define IRQ_IN_L3 0x0B 309 #define IRQ_XCS_L0 0x0C 310 #define IRQ_XCS_L1 0x0D 311 #define IRQ_XCS_L2 0x0E 312 #define IRQ_DOORBELL 0x0F 313 #define IRQ_DMA_1 0x10 314 #define IRQ_DMA_2 0x11 316 #define IRQ_PMCSR 0x13 317 #define IRQ_RESERVED1 0x14 318 #define IRQ_RESERVED2 0x15 319 #define IRQ_BIST 0x16 320 #define IRQ_SERR 0x17 321 #define IRQ_SDRAM_PARITY 0x18 323 #define IRQ_RESERVED3 0x1A 324 #define IRQ_DISCARD_TIMER 0x1B 325 #define IRQ_DATA_PARITY 0x1C 326 #define IRQ_MASTER_ABORT 0x1D 327 #define IRQ_TARGET_ABORT 0x1E 328 #define IRQ_PARITY 0x1F 332 #define IRQ_STATUS 0x180 333 #define IRQ_RAW_STATUS 0x184 334 #define IRQ_ENABLE 0x188 335 #define IRQ_ENABLE_SET 0x188 336 #define IRQ_ENABLE_CLEAR 0x18c 337 #define IRQ_SOFT 0x190 339 #define FIQ_STATUS 0x280 340 #define FIQ_RAW_STATUS 0x284 341 #define FIQ_ENABLE 0x288 342 #define FIQ_ENABLE_SET 0x288 343 #define FIQ_ENABLE_CLEAR 0x28c 344 #define FIQ_SOFT 0x290 350 #define TIMER_LOAD 0x00 351 #define TIMER_VALUE 0x04 352 #define TIMER_CONTROL 0x08 353 #define TIMER_CLEAR 0x0C 354 #define TIMER_1_BASE 0x300 355 #define TIMER_2_BASE 0x320 356 #define TIMER_3_BASE 0x340 357 #define TIMER_4_BASE 0x360 361 #define TIMER_FCLK 0x00 362 #define TIMER_FCLK_16 0x04 363 #define TIMER_FCLK_256 0x08 364 #define TIMER_EXTERNAL 0x0C 365 #define TIMER_MODE_FREERUN 0x00 366 #define TIMER_MODE_PERIODIC 0x40 367 #define TIMER_ENABLE 0x80 371 #define TIMER_MAX_VAL 0x00FFFFFF 375 #define TIMER_1_LOAD 0x300 376 #define TIMER_1_VALUE 0x304 377 #define TIMER_1_CONTROL 0x308 378 #define TIMER_1_CLEAR 0x30C 379 #define TIMER_2_LOAD 0x320 380 #define TIMER_2_VALUE 0x324 381 #define TIMER_2_CONTROL 0x328 382 #define TIMER_2_CLEAR 0x32C 383 #define TIMER_3_LOAD 0x340 384 #define TIMER_3_VALUE 0x344 385 #define TIMER_3_CONTROL 0x348 386 #define TIMER_3_CLEAR 0x34C 387 #define TIMER_4_LOAD 0x360 388 #define TIMER_4_VALUE 0x364 389 #define TIMER_4_CONTROL 0x368 390 #define TIMER_4_CLEAR 0x36C 395 #define FCLK 50000000
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