comreg.h Source File

Back to the index.

comreg.h
Go to the documentation of this file.
1 /* gxemul: $Id: comreg.h,v 1.3 2005-03-05 12:34:02 debug Exp $ */
2 #ifndef COMREG_H
3 #define COMREG_H
4 
5 /* $NetBSD: comreg.h,v 1.11 1997/10/19 14:26:21 fvdl Exp $ */
6 
7 /*-
8  * Copyright (c) 1991 The Regents of the University of California.
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  * notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  * notice, this list of conditions and the following disclaimer in the
18  * documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  * must display the following acknowledgement:
21  * This product includes software developed by the University of
22  * California, Berkeley and its contributors.
23  * 4. Neither the name of the University nor the names of its contributors
24  * may be used to endorse or promote products derived from this software
25  * without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  *
39  * @(#)comreg.h 7.2 (Berkeley) 5/9/91
40  */
41 
42 #include "ns16550reg.h"
43 
44 #define COM_FREQ 1843200 /* 16-bit baud rate divisor */
45 #define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
46 
47 /* interrupt enable register */
48 #define IER_ERXRDY 0x1 /* Enable receiver interrupt */
49 #define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */
50 #define IER_ERLS 0x4 /* Enable line status interrupt */
51 #define IER_EMSC 0x8 /* Enable modem status interrupt */
52 #define IER_ERTS 0x40 /* Enable RTS interrupt */
53 #define IER_ECTS 0x80 /* Enable CTS interrupt */
54 
55 /* interrupt identification register */
56 #define IIR_IMASK 0xf
57 #define IIR_RXTOUT 0xc
58 #define IIR_RLS 0x6 /* Line status change */
59 #define IIR_RXRDY 0x4 /* Receiver ready */
60 #define IIR_TXRDY 0x2 /* Transmitter ready */
61 #define IIR_MLSC 0x0 /* Modem status */
62 #define IIR_NOPEND 0x1 /* No pending interrupts */
63 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
64 
65 /* fifo control register */
66 #define FIFO_ENABLE 0x01 /* Turn the FIFO on */
67 #define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
68 #define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
69 #define FIFO_DMA_MODE 0x08
70 #define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
71 #define FIFO_TRIGGER_4 0x40 /* ibid 4 */
72 #define FIFO_TRIGGER_8 0x80 /* ibid 8 */
73 #define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
74 
75 /* enhanced feature register */
76 #define EFR_AUTOCTS 0x80 /* Automatic CTS flow control */
77 #define EFR_AUTORTS 0x40 /* Automatic RTS flow control */
78 #define EFR_SPECIAL 0x20 /* Special char detect */
79 #define EFR_EFCR 0x10 /* Enhanced function control bit */
80 #define EFR_TXFLOWBOTH 0x0c /* Automatic transmit XON/XOFF 1 and 2 */
81 #define EFR_TXFLOW1 0x08 /* Automatic transmit XON/XOFF 1 */
82 #define EFR_TXFLOW2 0x04 /* Automatic transmit XON/XOFF 2 */
83 #define EFR_TXFLOWNONE 0x00 /* No automatic XON/XOFF transmit */
84 #define EFR_RXFLOWBOTH 0x03 /* Automatic receive XON/XOFF 1 and 2 */
85 #define EFR_RXFLOW1 0x02 /* Automatic receive XON/XOFF 1 */
86 #define EFR_RXFLOW2 0x01 /* Automatic receive XON/XOFF 2 */
87 #define EFR_RXFLOWNONE 0x00 /* No automatic XON/XOFF receive */
88 
89 /* line control register */
90 #define LCR_EERS 0xBF /* Enable access to Enhanced Register Set */
91 #define LCR_DLAB 0x80 /* Divisor latch access enable */
92 #define LCR_SBREAK 0x40 /* Break Control */
93 #define LCR_PZERO 0x38 /* Space parity */
94 #define LCR_PONE 0x28 /* Mark parity */
95 #define LCR_PEVEN 0x18 /* Even parity */
96 #define LCR_PODD 0x08 /* Odd parity */
97 #define LCR_PNONE 0x00 /* No parity */
98 #define LCR_PENAB 0x08 /* XXX - low order bit of all parity */
99 #define LCR_STOPB 0x04 /* 2 stop bits per serial word */
100 #define LCR_8BITS 0x03 /* 8 bits per serial word */
101 #define LCR_7BITS 0x02 /* 7 bits */
102 #define LCR_6BITS 0x01 /* 6 bits */
103 #define LCR_5BITS 0x00 /* 5 bits */
104 
105 /* modem control register */
106 #define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */
107 #define MCR_IENABLE 0x08 /* Out2: enables UART interrupts */
108 #define MCR_DRS 0x04 /* Out1: resets some internal modems */
109 #define MCR_RTS 0x02 /* Request To Send */
110 #define MCR_DTR 0x01 /* Data Terminal Ready */
111 
112 /* line status register */
113 #define LSR_RCV_FIFO 0x80
114 #define LSR_TSRE 0x40 /* Transmitter empty: byte sent */
115 #define LSR_TXRDY 0x20 /* Transmitter buffer empty */
116 #define LSR_BI 0x10 /* Break detected */
117 #define LSR_FE 0x08 /* Framing error: bad stop bit */
118 #define LSR_PE 0x04 /* Parity error */
119 #define LSR_OE 0x02 /* Overrun, lost incoming byte */
120 #define LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */
121 #define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */
122 
123 /* modem status register */
124 /* All deltas are from the last read of the MSR. */
125 #define MSR_DCD 0x80 /* Current Data Carrier Detect */
126 #define MSR_RI 0x40 /* Current Ring Indicator */
127 #define MSR_DSR 0x20 /* Current Data Set Ready */
128 #define MSR_CTS 0x10 /* Current Clear to Send */
129 #define MSR_DDCD 0x08 /* DCD has changed state */
130 #define MSR_TERI 0x04 /* RI has toggled low to high */
131 #define MSR_DDSR 0x02 /* DSR has changed state */
132 #define MSR_DCTS 0x01 /* CTS has changed state */
133 
134 /* XXX ISA-specific. */
135 #define COM_NPORTS 8
136 
137 #endif /* COMREG_H */

Generated on Fri Dec 7 2018 19:52:23 for GXemul by doxygen 1.8.13