dev_pcic.cc Source File

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dev_pcic.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Intel 82365SL PC Card Interface Controller
29  *
30  * (Called "pcic" by NetBSD.)
31  *
32  * TODO: Lots of stuff. This is just a quick hack. Don't rely on it.
33  */
34 
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 
39 #include "cpu.h"
40 #include "device.h"
41 #include "emul.h"
42 #include "interrupt.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46 
47 #include "thirdparty/i82365reg.h"
48 #include "thirdparty/pcmciareg.h"
49 
50 
51 /* #define debug fatal */
52 
53 #define DEV_PCIC_LENGTH 2
54 
55 struct pcic_data {
56  struct interrupt irq;
57  int regnr;
58 };
59 
60 
61 DEVICE_ACCESS(pcic_cis)
62 {
63  /* struct pcic_data *d = (struct pcic_data *) extra; */
64  uint64_t idata = 0, odata = 0;
65 
66  idata = memory_readmax64(cpu, data, len);
67 
68 {
69 #if 0
70  /* SMC, PCM Ethernet Adapter, CIS V1.05 (manufacturer 0x108,
71  product 0x105) */
72  unsigned char x[] = {
74  PCMCIA_CISTPL_FUNCID, 2, 0x06, 0x00,
75  PCMCIA_CISTPL_MANFID, 4, 0x08, 0x01, 0x05, 0x01,
77  0x04, 0x01, 0x53, 0x4d, 0x43, 0x00, 0x50, 0x43, 0x4d, 0x20,
78  0x45, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x20, 0x41,
79  0x64, 0x61, 0x70, 0x74, 0x65, 0x72, 0x00, 0x43, 0x49, 0x53,
80  0x20, 0x56, 0x31, 0x2e, 0x30, 0x35, 0x00, 0xff,
82  0x02, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0xff,
84  0xc1, 0x01, 0x70, 0x50, 0xbc, 0x8e, 0x48, 0x40, 0x00,0x02,0xff,
85  /* unhandled CISTPL 22 */
86  0x22, 0x02, 0x01, 0x02,
87  /* unhandled CISTPL 22 */
88  0x22, 0x05, 0x02, 0x80, 0x96, 0x98, 0x00,
89  /* unhandled CISTPL 22 */
90  0x22, 0x02, 0x03, 0x01,
91  /* unhandled CISTPL 22 */
92  0x22, 0x08, 0x04, 0x06, 0x00, 0x00, 0xc0, 0x2f, 0x48, 0xd2,
93  /* unhandled CISTPL 22 */
94  0x22, 0x02, 0x05, 0x01,
95 
97  };
98 #endif
99 
100  /* From http://www.mail-archive.com/freebsd-current@freebsd.
101  org/msg32550.html */
102  unsigned char x[] = {
103  PCMCIA_CISTPL_DEVICE, 3, 0xdc, 0x00, 0xff,
104  PCMCIA_CISTPL_VERS_1, 0x1a,
105  0x04,0x01,0x20,0x00,0x4e,0x69,0x6e,0x6a,0x61,0x41,0x54,0x41,
106  0x2d,0x00,0x56,0x31,0x2e,0x30,0x00,0x41,0x50,0x30,0x30,0x20,
107  0x00,0xff,
109  0x01,0x23,0x00,0x02,0x03,
111  0xe1,0x01,0x3d,0x11,0x55,0x1e,0xfc,0x23,0xf0,0x61,0x80,0x01,
112  0x07,0x86,0x03,0x01,0x30,0x68,0xd0,0x10,0x00,
113 #if 0
115  0x22,0x38,0xf0,0x61,0x90,0x01,0x07,0x96,0x03,0x01,0x30,0x68,
116  0xd0,0x10,0x00,
118  0x23,0x38,0xf0,0x61,0xa0,0x01,0x07,0xa6,0x03,0x01,0x30,0x68,
119  0xd0,0x10,0x00,
120 #endif
122 
124  };
125 
126  relative_addr /= 2;
127  if (relative_addr < sizeof(x))
128  odata = x[relative_addr];
129 
130  debug("[ dev_pcic_cis_access: blah blah: addr=0x%x ]\n",
131  (int)relative_addr);
132 }
133 
134  if (writeflag == MEM_READ)
135  memory_writemax64(cpu, data, len, odata);
136 
137  return 1;
138 }
139 
140 
142 {
143  struct pcic_data *d = (struct pcic_data *) extra;
144  uint64_t idata = 0, odata = 0;
145  int controller_nr, socket_nr;
146 
147  if (writeflag == MEM_WRITE)
148  idata = memory_readmax64(cpu, data, len);
149 
150  controller_nr = d->regnr & 0x80? 1 : 0;
151  socket_nr = d->regnr & 0x40? 1 : 0;
152 
153  switch (relative_addr) {
154 
155  case 0: /* Register select: */
156  if (writeflag == MEM_WRITE)
157  d->regnr = idata;
158  else
159  odata = d->regnr;
160  break;
161 
162  case 1: /* Register access: */
163  switch (d->regnr & 0x3f) {
164 
165  case PCIC_IDENT:
166  /* This causes sockets A and B to be present on
167  controller 0, and only socket A on controller 1. */
168  if (controller_nr == 1 && socket_nr == 1)
169  odata = 0;
170  else
173  break;
174 #if 1
175  case PCIC_INTR:
176  odata = PCIC_INTR_IRQ3;
177  break;
178 #endif
179 
180  case PCIC_CSC:
181  odata = PCIC_CSC_GPI;
182  break;
183 
184  case PCIC_IF_STATUS:
185  odata = PCIC_IF_STATUS_READY
187  if (controller_nr == 0 && socket_nr == 0)
189  break;
190 
191  default:
192  if (writeflag == MEM_WRITE) {
193  debug("[ pcic: unimplemented write to "
194  "controller %i socket %c, regnr %i: "
195  "data=0x%02x ]\n", controller_nr,
196  socket_nr? 'B' : 'A',
197  d->regnr & 0x3f, (int)idata);
198  } else {
199  debug("[ pcic: unimplemented read from "
200  "controller %i socket %c, regnr %i ]\n",
201  controller_nr, socket_nr? 'B' : 'A',
202  d->regnr & 0x3f);
203  }
204  }
205  }
206 
207  if (writeflag == MEM_READ)
208  memory_writemax64(cpu, data, len, odata);
209 
210  return 1;
211 }
212 
213 
214 DEVINIT(pcic)
215 {
216  char tmpstr[200];
217  struct pcic_data *d;
218 
219  CHECK_ALLOCATION(d = (struct pcic_data *) malloc(sizeof(struct pcic_data)));
220  memset(d, 0, sizeof(struct pcic_data));
221 
223 
226  dev_pcic_access, (void *)d, DM_DEFAULT, NULL);
227 
228  /* TODO: this shouldn't be hardcoded for hpcmips here! */
230  0x10070000, 0x1000, dev_pcic_cis_access, (void *)d,
231  DM_DEFAULT, NULL);
232 
233  /* TODO: find out a good way to specify the address, and the IRQ! */
234  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x14000180 irq=%s.giu.9",
236  device_add(devinit->machine, tmpstr);
237 
238  /* TODO: Linux/MobilePro looks at 0x14000170 and 0x1f0... */
239  /* Yuck. Now there are two. How should this be solved nicely? */
240  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x140001f0 irq=%s.giu.9",
242  device_add(devinit->machine, tmpstr);
243 
244  return 1;
245 }
246 
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
#define PCIC_IDENT_IFTYPE_MEM_AND_IO
Definition: i82365reg.h:63
#define DM_DEFAULT
Definition: memory.h:130
#define PCMCIA_CISTPL_CFTABLE_ENTRY
Definition: pcmciareg.h:100
#define PCMCIA_CISTPL_DEVICE
Definition: pcmciareg.h:46
DEVICE_ACCESS(pcic_cis)
Definition: dev_pcic.cc:61
#define PCIC_IDENT
Definition: i82365reg.h:59
#define PCMCIA_CISTPL_END
Definition: pcmciareg.h:186
char * name
Definition: device.h:43
#define PCIC_IF_STATUS
Definition: i82365reg.h:77
#define PCIC_IF_STATUS_CARDDETECT_PRESENT
Definition: i82365reg.h:83
#define MEM_READ
Definition: memory.h:116
#define PCMCIA_CISTPL_VERS_1
Definition: pcmciareg.h:88
struct memory * memory
Definition: machine.h:126
#define PCMCIA_CISTPL_MANFID
Definition: pcmciareg.h:164
void * device_add(struct machine *machine, const char *name_and_params)
Definition: device.cc:252
#define PCMCIA_CISTPL_CONFIG
Definition: pcmciareg.h:93
DEVINIT(pcic)
Definition: dev_pcic.cc:214
#define DEV_PCIC_LENGTH
Definition: dev_pcic.cc:53
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
struct interrupt irq
Definition: dev_pcic.cc:56
#define PCMCIA_CISTPL_FUNCID
Definition: pcmciareg.h:165
u_short data
Definition: siireg.h:79
#define PCIC_IF_STATUS_READY
Definition: i82365reg.h:80
#define PCIC_IF_STATUS_POWERACTIVE
Definition: i82365reg.h:79
#define MEM_WRITE
Definition: memory.h:117
#define PCIC_CSC
Definition: i82365reg.h:106
Definition: device.h:40
#define debug
Definition: dev_adb.cc:57
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
struct machine * machine
Definition: device.h:41
#define PCIC_INTR_IRQ3
Definition: i82365reg.h:149
#define PCMCIA_DTYPE_FUNCSPEC
Definition: pcmciareg.h:56
#define PCMCIA_CISTPL_NO_LINK
Definition: pcmciareg.h:87
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
int regnr
Definition: dev_pcic.cc:57
uint64_t addr
Definition: device.h:46
#define PCIC_CSC_GPI
Definition: i82365reg.h:108
#define PCIC_IDENT_REV_I82365SLR1
Definition: i82365reg.h:68
#define PCIC_INTR
Definition: i82365reg.h:137
char * interrupt_path
Definition: device.h:50

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