63 int IB, DB, SB,
IC, DC, SC, IA, DA;
86 IB = IB < 0? 0 : (IB > 7? 7 : IB);
88 DB = DB < 0? 0 : (DB > 7? 7 : DB);
121 IB = IB < 0? 0 : (IB > 1? 1 : IB);
123 DB = DB < 0? 0 : (DB > 1? 1 : DB);
125 SB = SB < 0? 0 : (SB > 3? 3 : SB);
127 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
129 DC = DC < 0? 0 : (DC > 7? 7 : DC);
163 IB = IB < 0? 0 : (IB > 1? 1 : IB);
165 DB = DB < 0? 0 : (DB > 1? 1 : DB);
167 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
169 DC = DC < 0? 0 : (DC > 7? 7 : DC);
234 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
236 DC = DC < 0? 0 : (DC > 7? 7 : DC);
238 SC = SC < 0? 0 : (SC > 7? 7 : SC);
302 default:
fatal(
"Internal error: No initialization code for" 314 static void initialize_cop1(
struct cpu *cpu,
struct mips_coproc *c)
317 uint64_t other_stuff = 0;
365 if (coproc_nr == 0) {
402 initialize_cop0_config(cpu, c);
409 initialize_cop1(cpu, c);
418 static void mips_timer_tick(
struct timer *
timer,
void *extra)
420 struct cpu *cpu = (
struct cpu *) extra;
439 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
440 int valid0,
int valid1,
int dirty0,
int dirty1,
int global,
int asid,
441 int cachealgo0,
int cachealgo1)
444 printf(
"mips_coproc_tlb_set_entry(): invalid entry nr: %i\n",
452 printf(
"mips_coproc_tlb_set_entry(): invalid pagesize " 453 "(%i) for MMU3K\n", size);
478 (vaddr & ENTRYHI_R_MASK) |
483 (2*size - 1) & ~0x1fff;
494 (dirty1? ENTRYLO_D : 0) |
496 (global? ENTRYLO_G : 0) |
512 static void invalidate_asid(
struct cpu *cpu,
unsigned int asid)
519 for (i = 0; i < ntlbs; i++)
528 for (i = 0; i < ntlbs; i++) {
533 uint64_t pagesize = 0x1000;
534 uint64_t tmp = mask >> 13;
543 oldvaddr = cp->
tlbs[i].
hi &
546 if (oldvaddr & 0x80000000000ULL)
547 oldvaddr |= 0x3ffff00000000000ULL;
551 oldvaddr = (int32_t)oldvaddr;
554 oldvaddr = cp->
tlbs[i].
hi &
557 if (oldvaddr & 0x8000000000ULL)
558 oldvaddr |= 0x3fffff0000000000ULL;
567 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
570 if (cp->
tlbs[i].
lo1 & ENTRYLO_V)
571 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
584 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int select)
613 default:
fatal(
"coproc_register_read(): unimplemented" 614 " config register select %i\n", select);
641 fatal(
"cpu%i: warning: read from unimplemented coproc%i" 643 cp->
coproc_nr==0? cop0_names[reg_nr] :
"?");
650 *ptr = cp->
reg[reg_nr];
660 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int flag64,
666 uint64_t tmp2 = 0, old;
668 unsigned int old_asid;
740 fatal(
"[ cpu%i: trying to write an invalid" 741 " pagemask 0x%08lx to COP0_PAGEMASK ]\n",
747 fatal(
"[ cpu%i: r2k/r3k wired register must " 748 "always be 8 ]\n", cpu->
cpu_id);
756 if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
757 fatal(
"[ WARNING: trying to write a 64-bit value" 758 " to the COUNT register! ]\n");
759 tmp = (int64_t)(int32_t)tmp;
764 int32_t compare_diff = tmp -
768 if (compare_diff < 0)
771 if (compare_diff == 0)
775 / (
double)compare_diff;
781 hz, mips_timer_tick, cpu);
796 if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
797 fatal(
"[ WARNING: trying to write a 64-bit value" 798 " to the COMPARE register! ]\n");
800 tmp = (int64_t)(int32_t)tmp;
827 invalidate_asid(cpu, old_asid);
866 default:
fatal(
"[ coproc_register_write(): unimpl" 867 "emented config register select " 878 cp->
reg[reg_nr] &= ~(0x3); cp->
reg[reg_nr] |= tmp;
897 if (tmp & MIPS1_ISOL_CACHES) {
956 fatal(
"[ cpu%i: warning: write to unimplemented coproc%i " 957 "register %i (%s), data = 0x%016llx ]\n", cpu->
cpu_id,
959 cop0_names[reg_nr] :
"?", (
long long)tmp);
967 fatal(
"[ cpu%i: warning: write to READONLY coproc%i register " 972 cp->
reg[reg_nr] = tmp;
975 cp->
reg[reg_nr] = (int64_t)(int32_t)cp->
reg[reg_nr];
984 static int mips_fmt_to_ieee_fmt[32] = {
985 0, 0, 0, 0, 0, 0, 0, 0,
986 0, 0, 0, 0, 0, 0, 0, 0,
989 0, 0, 0, 0, 0, 0, 0, 0 };
991 static const char *fmtname[32] = {
992 "0",
"1",
"2",
"3",
"4",
"5",
"6",
"7",
993 "8",
"9",
"10",
"11",
"12",
"13",
"14",
"15",
994 "s",
"d",
"18",
"19",
"w",
"l",
"ps",
"23",
995 "24",
"25",
"26",
"27",
"28",
"29",
"30",
"31" };
997 static const char *ccname[16] = {
998 "f",
"un",
"eq",
"ueq",
"olt",
"ult",
"ole",
"ule",
999 "sf",
"ngle",
"seq",
"ngl",
"lt",
"nge",
"le",
"ngt" };
1001 #define FPU_OP_ADD 1 1002 #define FPU_OP_SUB 2 1003 #define FPU_OP_MUL 3 1004 #define FPU_OP_DIV 4 1005 #define FPU_OP_SQRT 5 1006 #define FPU_OP_MOV 6 1007 #define FPU_OP_CVT 7 1009 #define FPU_OP_ABS 9 1010 #define FPU_OP_NEG 10 1019 static void fpu_store_float_value(
bool fr,
struct mips_coproc *cp,
int fd,
1020 double nf,
int fmt,
int nan)
1022 int ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
1033 cp->
reg[fd] = r & 0xffffffffULL;
1034 cp->
reg[(fd+1) & 31] = (r >> 32) & 0xffffffffULL;
1036 if (cp->
reg[fd] & 0x80000000ULL)
1037 cp->
reg[fd] |= 0xffffffff00000000ULL;
1038 if (cp->
reg[fd+1] & 0x80000000ULL)
1039 cp->
reg[fd+1] |= 0xffffffff00000000ULL;
1042 cp->
reg[fd] = r & 0xffffffffULL;
1044 if (cp->
reg[fd] & 0x80000000ULL)
1045 cp->
reg[fd] |= 0xffffffff00000000ULL;
1059 static int fpu_op(
struct cpu *cpu,
struct mips_coproc *cp,
int op,
int fmt,
1060 int ft,
int fs,
int fd,
int cond,
int output_fmt)
1064 int unordered,
nan, ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
1075 fs_v = (fs_v & 0xffffffffULL) +
1076 (cp->
reg[(fs + 1) & 31] << 32);
1082 uint64_t v = cp->
reg[ft];
1085 v = (v & 0xffffffffULL) +
1086 (cp->
reg[(ft + 1) & 31] << 32);
1095 nf = float_value[0].
f + float_value[1].
f;
1098 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1099 float_value[0].nan || float_value[1].nan);
1102 nf = float_value[0].
f - float_value[1].
f;
1105 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1106 float_value[0].nan || float_value[1].nan);
1109 nf = float_value[0].
f * float_value[1].
f;
1112 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1113 float_value[0].nan || float_value[1].nan);
1116 nan = float_value[0].
nan || float_value[1].
nan;
1117 if (fabs(float_value[1].
f) > 0.00000000001)
1118 nf = float_value[0].
f / float_value[1].
f;
1120 fatal(
"DIV by zero !!!! TODO\n");
1128 fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
1131 nan = float_value[0].
nan;
1132 if (float_value[0].f >= 0.0)
1133 nf = sqrt(float_value[0].f);
1135 fatal(
"SQRT by less than zero, %f !!!!\n",
1141 fpu_store_float_value(fr, cp, fd, nf, output_fmt, nan);
1144 nf = fabs(float_value[0].f);
1146 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1147 float_value[0].nan);
1150 nf = - float_value[0].
f;
1152 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1153 float_value[0].nan);
1156 nf = float_value[0].
f;
1158 fpu_store_float_value(fr, cp, fd, nf, output_fmt,
1159 float_value[0].nan);
1171 cp->
reg[fd] = fs_v & 0xffffffffULL;
1172 cp->
reg[(fd+1) & 31] = (fs_v >> 32) & 0xffffffffULL;
1173 if (cp->
reg[fd] & 0x80000000ULL)
1174 cp->
reg[fd] |= 0xffffffff00000000ULL;
1175 if (cp->
reg[fd+1] & 0x80000000ULL)
1176 cp->
reg[fd+1] |= 0xffffffff00000000ULL;
1179 cp->
reg[fd] = fs_v & 0xffffffffULL;
1180 if (cp->
reg[fd] & 0x80000000ULL)
1181 cp->
reg[fd] |= 0xffffffff00000000ULL;
1188 if (float_value[0].nan || float_value[1].nan)
1193 return (float_value[0].f == float_value[1].f);
1195 return (float_value[0].f < float_value[1].f)
1198 return (float_value[0].f < float_value[1].f)
1201 return (float_value[0].f <= float_value[1].f)
1204 return (float_value[0].f <= float_value[1].f)
1207 return (float_value[0].f < float_value[1].f);
1209 return (float_value[0].f <= float_value[1].f);
1216 case 3:
return (float_value[0].f == float_value[1].f);
1220 case 10:
return (float_value[0].f == float_value[1].f);
1221 case 11:
return (float_value[0].f == float_value[1].f);
1223 case 13:
return !(float_value[0].
f >= float_value[1].
f);
1225 case 15:
return !(float_value[0].
f > float_value[1].
f);
1229 fatal(
"fpu_op(): unimplemented condition " 1230 "code %i. see cpu_mips_coproc.c\n", cond);
1234 fatal(
"fpu_op(): unimplemented op %i\n", op);
1247 static int fpu_function(
struct cpu *cpu,
struct mips_coproc *cp,
1248 uint32_t
function,
int unassemble_only)
1250 int fd, fs, ft, fmt,
cond, cc;
1252 fmt = (
function >> 21) & 31;
1253 ft = (
function >> 16) & 31;
1254 fs = (
function >> 11) & 31;
1255 cc = (
function >> 8) & 7;
1256 fd = (
function >> 6) & 31;
1257 cond = (
function >> 0) & 15;
1261 if ((
function & 0x03e00000) == 0x01000000) {
1263 const char *instr_mnem;
1266 cc = (
function >> 18) & 7;
1267 nd = (
function >> 17) & 1;
1268 tf = (
function >> 16) & 1;
1269 imm =
function & 65535;
1274 if (nd == 0 && tf == 0) instr_mnem =
"bc1f";
1275 if (nd == 0 && tf == 1) instr_mnem =
"bc1t";
1276 if (nd == 1 && tf == 0) instr_mnem =
"bc1fl";
1277 if (nd == 1 && tf == 1) instr_mnem =
"bc1tl";
1280 debug(
"%s\t%i,0x%016llx\n", instr_mnem, cc,
1281 (
long long) (cpu->
pc + 4 + (imm << 2)));
1282 if (unassemble_only)
1285 fatal(
"INTERNAL ERROR: MIPS coprocessor branches should not" 1286 " be implemented in cpu_mips_coproc.c, but in" 1287 " cpu_mips_instr.c!\n");
1292 if ((
function & 0x0000003f) == 0x00000000) {
1294 debug(
"add.%s\tr%i,r%i,r%i\n",
1295 fmtname[fmt], fd, fs, ft);
1296 if (unassemble_only)
1299 fpu_op(cpu, cp,
FPU_OP_ADD, fmt, ft, fs, fd, -1, fmt);
1304 if ((
function & 0x0000003f) == 0x00000001) {
1306 debug(
"sub.%s\tr%i,r%i,r%i\n",
1307 fmtname[fmt], fd, fs, ft);
1308 if (unassemble_only)
1311 fpu_op(cpu, cp,
FPU_OP_SUB, fmt, ft, fs, fd, -1, fmt);
1316 if ((
function & 0x0000003f) == 0x00000002) {
1318 debug(
"mul.%s\tr%i,r%i,r%i\n",
1319 fmtname[fmt], fd, fs, ft);
1320 if (unassemble_only)
1323 fpu_op(cpu, cp,
FPU_OP_MUL, fmt, ft, fs, fd, -1, fmt);
1328 if ((
function & 0x0000003f) == 0x00000003) {
1330 debug(
"div.%s\tr%i,r%i,r%i\n",
1331 fmtname[fmt], fd, fs, ft);
1332 if (unassemble_only)
1335 fpu_op(cpu, cp,
FPU_OP_DIV, fmt, ft, fs, fd, -1, fmt);
1340 if ((
function & 0x001f003f) == 0x00000004) {
1342 debug(
"sqrt.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1343 if (unassemble_only)
1346 fpu_op(cpu, cp,
FPU_OP_SQRT, fmt, -1, fs, fd, -1, fmt);
1351 if ((
function & 0x001f003f) == 0x00000005) {
1353 debug(
"abs.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1354 if (unassemble_only)
1357 fpu_op(cpu, cp,
FPU_OP_ABS, fmt, -1, fs, fd, -1, fmt);
1362 if ((
function & 0x0000003f) == 0x00000006) {
1364 debug(
"mov.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1365 if (unassemble_only)
1368 fpu_op(cpu, cp,
FPU_OP_MOV, fmt, -1, fs, fd, -1, fmt);
1373 if ((
function & 0x001f003f) == 0x00000007) {
1375 debug(
"neg.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1376 if (unassemble_only)
1379 fpu_op(cpu, cp,
FPU_OP_NEG, fmt, -1, fs, fd, -1, fmt);
1384 if ((
function & 0x001f003f) == 0x00000009) {
1386 debug(
"trunc.l.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1387 if (unassemble_only)
1397 if ((
function & 0x001f003f) == 0x0000000d) {
1399 debug(
"trunc.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1400 if (unassemble_only)
1410 if ((
function & 0x000000f0) == 0x00000030) {
1415 debug(
"c.%s.%s\tcc%i,r%i,r%i\n", ccname[cond],
1416 fmtname[fmt], cc, fs, ft);
1417 if (unassemble_only)
1420 cond_true = fpu_op(cpu, cp,
FPU_OP_C, fmt,
1421 ft, fs, -1, cond, fmt);
1448 if ((
function & 0x001f003f) == 0x00000020) {
1450 debug(
"cvt.s.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1451 if (unassemble_only)
1459 if ((
function & 0x001f003f) == 0x00000021) {
1461 debug(
"cvt.d.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1462 if (unassemble_only)
1470 if ((
function & 0x001f003f) == 0x00000024) {
1472 debug(
"cvt.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1473 if (unassemble_only)
1492 int i, found, g_bit;
1493 uint64_t vpn2, xmask;
1502 fatal(
"[ warning: tlbr from index %i (too " 1514 fatal(
"[ warning: tlbr from index %i (too " 1575 uint64_t a = vpn2 & ~cp->
tlbs[i].
mask;
1576 uint64_t b = (cp->
tlbs[i].
hi & xmask) &
1599 0xffffffff00000000ULL;
1636 fatal(
"warning: tlb index %i too high (max is %i)\n",
1645 fatal(
"{ old TLB entry at index %02x:", index);
1647 fatal(
" hi=%08" PRIx32, (uint32_t)cp->
tlbs[index].
hi);
1648 fatal(
" lo=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo0);
1652 fatal(
" hi=%08" PRIx32, (uint32_t)cp->
tlbs[index].
hi);
1653 fatal(
" lo0=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo0);
1654 fatal(
" lo1=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo1);
1678 oldvaddr = (int32_t) oldvaddr;
1690 oldvaddr = cp->
tlbs[index].
hi &
1693 if (oldvaddr & 0x80000000000ULL)
1694 oldvaddr |= 0x3ffff00000000000ULL;
1698 oldvaddr = (int32_t)oldvaddr;
1701 oldvaddr = cp->
tlbs[index].
hi &
1704 if (oldvaddr & 0x8000000000ULL)
1705 oldvaddr |= 0x3fffff0000000000ULL;
1709 uint64_t mask = cp->
tlbs[index].
mask;
1710 uint64_t pagesize = 0x1000;
1711 uint64_t tmp = mask >> 13;
1723 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
1726 if (cp->
tlbs[index].
lo1 & ENTRYLO_V)
1727 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
1743 uint64_t vaddr1, vaddr2;
1754 if (i == index && !randomflag)
1761 vaddr2 = cp->
tlbs[i].
hi &
1763 if (vaddr1 == vaddr2 && ((cp->
tlbs[i].
lo0 &
1765 fatal(
"\n[ WARNING! tlbw%s to index 0x%02x " 1766 "vaddr=0x%llx (asid 0x%02x) is already in" 1767 " the TLB (entry 0x%02x) ! ]\n\n",
1768 randomflag?
"r" :
"i", index,
1769 (
long long)vaddr1, asid, i);
1777 uint32_t vaddr, paddr;
1779 unsigned char *memblock = NULL;
1800 fatal(
"Wow! Interesting case; tlbw* while caches" 1801 " are isolated. TODO\n");
1809 if (memblock != NULL &&
1815 unsigned char *memblock = NULL;
1816 int pfn_shift = 12, vpn_shift = 12;
1818 uint64_t vaddr0, vaddr1, paddr0, paddr1, ptmp;
1840 fatal(
"1KB pages don't work with dyntrans.\n");
1845 case 0x0001fff:
break;
1846 case 0x0007fff: vpn_shift = 14;
break;
1847 case 0x001ffff: vpn_shift = 16;
break;
1848 case 0x007ffff: vpn_shift = 18;
break;
1849 case 0x01fffff: vpn_shift = 20;
break;
1850 case 0x07fffff: vpn_shift = 22;
break;
1851 case 0x1ffffff: vpn_shift = 24;
break;
1852 case 0x7ffffff: vpn_shift = 26;
break;
1853 default:
fatal(
"Unimplemented MASK = 0x%016x\n", mask);
1857 pfn_shift = vpn_shift;
1861 >> vpn_shift << vpn_shift;
1864 >> vpn_shift << vpn_shift;
1867 vaddr0 = cp->
tlbs[index].
hi &
1870 if (vaddr0 & 0x80000000000ULL)
1871 vaddr0 |= 0x3ffff00000000000ULL;
1875 vaddr0 = (int32_t)vaddr0;
1878 vaddr0 = cp->
tlbs[index].
hi &
1881 if (vaddr0 & 0x8000000000ULL)
1882 vaddr0 |= 0x3fffff0000000000ULL;
1885 vaddr1 = vaddr0 | (1 << vpn_shift);
1907 psize = 1 << pfn_shift;
1910 for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
1915 for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
1930 if (psize == 0x1000) {
1977 uint32_t
function,
int unassemble_only,
int running)
1979 int co_bit,
op, rt, rd, fs, copz;
1983 if (unassemble_only) {
1984 debug(
"cop%i\t0x%08x (coprocessor not available)\n",
1985 cpnr, (
int)
function);
1988 fatal(
"[ pc=0x%016llx cop%i\t0x%08x (coprocessor not " 1989 "available)\n", (
long long)cpu->
pc, cpnr, (
int)
function);
2000 copz = (
function >> 21) & 31;
2001 rt = (
function >> 16) & 31;
2002 rd = (
function >> 11) & 31;
2004 if (cpnr < 2 && (((
function & 0x03e007f8) == (
COPz_MFCz << 21))
2005 || ((
function & 0x03e007f8) == (
COPz_DMFCz << 21)))) {
2006 if (unassemble_only) {
2008 cpnr, regnames[rt]);
2010 debug(
"%s", cop0_names[rd]);
2014 debug(
",%i", (
int)(
function & 7));
2019 rd, &tmpvalue,
function & 7);
2024 if (cpu->
cd.
mips.
gpr[rt] & 0x80000000ULL)
2025 cpu->
cd.
mips.
gpr[rt] |= 0xffffffff00000000ULL;
2030 if (cpnr < 2 && (((
function & 0x03e007f8) == (
COPz_MTCz << 21))
2031 || ((
function & 0x03e007f8) == (
COPz_DMTCz << 21)))) {
2032 if (unassemble_only) {
2034 cpnr, regnames[rt]);
2036 debug(
"%s", cop0_names[rd]);
2040 debug(
",%i", (
int)(
function & 7));
2047 tmpvalue &= 0xffffffffULL;
2048 if (tmpvalue & 0x80000000ULL)
2049 tmpvalue |= 0xffffffff00000000ULL;
2052 &tmpvalue, copz ==
COPz_DMTCz,
function & 7);
2056 if (cpnr <= 1 && (((
function & 0x03e007ff) == (
COPz_CFCz << 21))
2057 || ((
function & 0x03e007ff) == (
COPz_CTCz << 21)))) {
2060 rt = (
function >> 16) & 31;
2061 fs = (
function >> 11) & 31;
2062 if (unassemble_only) {
2063 debug(
"cfc%i\t%s,r%i\n", cpnr,
2072 rt = (
function >> 16) & 31;
2073 fs = (
function >> 11) & 31;
2074 if (unassemble_only) {
2075 debug(
"ctc%i\t%s,r%i\n", cpnr,
2082 fatal(
"[ warning: unimplemented ctc%i, " 2083 "0x%08x -> ctl reg %i ]\n", cpnr,
2088 fatal(
"[ Attempt to write to FPU " 2089 "control register 0 (?) ]\n");
2102 0x017fffffULL) | ((tmp & 1)
2104 | (((tmp & 0xfe) >> 1) <<
2110 0xffffff00ULL) | ((tmp >>
2133 if (fpu_function(cpu, cp,
function, unassemble_only))
2140 if ((
function & 0xfffff) ==
COP0_EI) {
2141 if (unassemble_only) {
2150 if ((
function & 0xfffff) ==
COP0_DI) {
2151 if (unassemble_only) {
2161 co_bit = (
function >> 25) & 1;
2165 if (!unassemble_only) {
2166 fatal(
"FATAL INTERNAL ERROR: Should be implemented" 2167 " with dyntrans instead.\n");
2173 if ((
function & 0x03e0ffdf) == 0x01606000) {
2174 debug(
"%ci",
function & 0x20?
'e' :
'd');
2176 debug(
"\t%s", regnames[rt]);
2182 op = (
function) & 0xff;
2197 debug(
"\tindex=%08llx",
2199 debug(
", random=%08llx",
2201 debug(
", mask=%016llx",
2203 debug(
", hi=%016llx",
2205 debug(
", lo0=%016llx",
2207 debug(
", lo1=%016llx\n",
2226 int code = (
function >> 6) & 0x7ffff;
2229 debug(
"\t0x%x", code);
2240 debug(
"hibernate\n");
2251 if (unassemble_only) {
2252 debug(
"decstation_r2020_writeback\n");
2259 if (unassemble_only) {
2260 debug(
"cop%i\t0x%08x (unimplemented)\n", cpnr, (
int)
function);
2264 fatal(
"cpu%i: UNIMPLEMENTED coproc%i function %08" PRIx32
" " 2266 (uint32_t)
function, cpu->
pc);
#define MIPS_REGISTER_NAMES
void * zeroed_alloc(size_t s)
void fatal(const char *fmt,...)
int cache_secondary_linesize
#define ENTRYHI_VPN2_MASK_R10K
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1)
#define COP1_REVISION_SINGLE
#define R2K3K_ENTRYHI_ASID_MASK
#define MIPS1_ISOL_CACHES
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
#define R2K3K_ENTRYLO_PFN_MASK
void coproc_tlbwri(struct cpu *cpu, int randomflag)
uint64_t fcr[N_MIPS_FCRS]
void f(int s, int func, int only_name)
#define R2K3K_INDEX_SHIFT
void ieee_interpret_float_value(uint64_t x, struct ieee_float_value *fvp, int fmt)
#define R2K3K_ENTRYHI_ASID_SHIFT
#define CONTEXT_BADVPN2_MASK_R4100
#define ENTRYHI_VPN2_MASK
int cache_pdcache_linesize
int32_t count_register_read_count
#define CHECK_ALLOCATION(ptr)
void timer_update_frequency(struct timer *t, double new_freq)
uint64_t reg[N_MIPS_COPROC_REGS]
int cache_picache_linesize
#define R2K3K_ENTRYHI_VPN_MASK
void coproc_eret(struct cpu *cpu)
int compare_interrupts_pending
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
#define ENTRYLO_PFN_SHIFT
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
#define R2K3K_RANDOM_SHIFT
struct mips_coproc * coproc[N_MIPS_COPROCS]
#define MIPS_FCSR_FCC0_SHIFT
#define CONTEXT_BADVPN2_MASK
void coproc_register_write(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
#define R2K3K_RANDOM_MASK
uint64_t cop0_config_select1
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
uint64_t gpr[N_MIPS_GPRS]
void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
uint64_t ieee_store_float_value(double nf, int fmt)
addr & if(addr >=0x24 &&page !=NULL)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
struct mips_cpu_type_def cpu_type
#define R2K3K_CONTEXT_BADVPN_MASK
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
#define MIPS_FCSR_FCC1_SHIFT
int last_written_tlb_index
void coproc_tlbpr(struct cpu *cpu, int readflag)
unsigned char * memory_paddr_to_hostaddr(struct memory *mem, uint64_t paddr, int writeflag)
#define COP1_REVISION_DOUBLE