49 #define M88K_PID(arn,vn) ((arn << M88K_ARN_SHIFT) | (vn << M88K_VN_SHIFT)) 51 #define M88K_CPU_TYPE_DEFS { \ 52 { "88100", 88100, M88K_PID(M88K_ARN_88100,3) }, \ 53 { "88110", 88110, M88K_PID(M88K_ARN_88110,0) }, \ 58 #define N_M88K_CONTROL_REGS 64 59 #define M88K_CR_NAMES { \ 60 "PID", "PSR", "EPSR", "SSBR", \ 61 "SXIP", "SNIP", "SFIP", "VBR", \ 62 "DMT0", "DMD0", "DMA0", "DMT1", \ 63 "DMD1", "DMA1", "DMT2", "DMD2", \ 64 "DMA2", "SR0", "SR1", "SR2", \ 65 "SR3", "CR21", "CR22", "CR23", \ 66 "CR24", "CR25", "CR26", "CR27", \ 67 "CR28", "CR29", "CR30", "CR31", \ 68 "CR32", "CR33", "CR34", "CR35", \ 69 "CR36", "CR37", "CR38", "CR39", \ 70 "CR40", "CR41", "CR42", "CR43", \ 71 "CR44", "CR45", "CR46", "CR47", \ 72 "CR48", "CR49", "CR50", "CR51", \ 73 "CR52", "CR53", "CR54", "CR55", \ 74 "CR56", "CR57", "CR58", "CR59", \ 75 "CR60", "CR61", "CR62", "CR63" } 79 #define M88K_CR_EPSR 2 80 #define M88K_CR_SSBR 3 81 #define M88K_CR_SXIP 4 82 #define M88K_CR_SNIP 5 83 #define M88K_CR_SFIP 6 85 #define M88K_CR_DMT0 8 86 #define M88K_CR_DMD0 9 87 #define M88K_CR_DMA0 10 88 #define M88K_CR_DMT1 11 89 #define M88K_CR_DMD1 12 90 #define M88K_CR_DMA1 13 91 #define M88K_CR_DMT2 14 92 #define M88K_CR_DMD2 15 93 #define M88K_CR_DMA2 16 94 #define M88K_CR_SR0 17 95 #define M88K_CR_SR1 18 96 #define M88K_CR_SR2 19 97 #define M88K_CR_SR3 20 100 #define M88K_CR_NAMES_197 { \ 101 "PID", "PSR", "EPSR", "SSBR", \ 102 "EXIP", "ENIP", "SFIP", "VBR", \ 103 "DMT0", "DMD0", "DMA0", "DMT1", \ 104 "DMD1", "DMA1", "DMT2", "DMD2", \ 105 "SRX", "SR0", "SR1", "SR2", \ 106 "SR3", "CR21", "CR22", "CR23", \ 107 "CR24", "ICMD", "ICTL", "ISAR", \ 108 "ISAP", "IUAP", "IIR", "IBP", \ 109 "IPPU", "IPPL", "ISR", "ILAR", \ 110 "IPAR", "CR37", "CR38", "CR39", \ 111 "DCMD", "DCTL", "DSAR", "DSAP", \ 112 "DUAP", "DIR", "DBP", "DPPU", \ 113 "DPPL", "DSR", "DLAR", "DPAR", \ 114 "CR52", "CR53", "CR54", "CR55", \ 115 "CR56", "CR57", "CR58", "CR59", \ 116 "CR60", "CR61", "CR62", "CR63" } 118 #define M88K_CR_EXIP 4 119 #define M88K_CR_ENIP 5 120 #define M88K_CR_SRX 16 121 #define M88K_CR_ICMD 25 122 #define M88K_CR_ICTL 26 123 #define M88K_CR_ISAR 27 124 #define M88K_CR_ISAP 28 125 #define M88K_CR_IUAP 29 126 #define M88K_CR_IIR 30 127 #define M88K_CR_IBP 31 128 #define M88K_CR_IPPU 32 129 #define M88K_CR_IPPL 33 130 #define M88K_CR_ISR 34 131 #define M88K_CR_ILAR 35 132 #define M88K_CR_IPAR 36 133 #define M88K_CR_DCMD 40 134 #define M88K_CR_DCTL 41 135 #define M88K_CR_DSAR 42 136 #define M88K_CR_DSAP 43 137 #define M88K_CR_DUAP 44 138 #define M88K_CR_DIR 45 139 #define M88K_CR_DBP 46 140 #define M88K_CR_DPPU 47 141 #define M88K_CR_DPPL 48 142 #define M88K_CR_DSR 49 143 #define M88K_CR_DLAR 50 144 #define M88K_CR_DPAR 51 147 #define N_M88K_FPU_CONTROL_REGS 64 149 #define M88K_FPCR_FPECR 0 150 #define M88K_FPECR_FDVZ (1 << 3) 151 #define M88K_FPECR_FUNIMP (1 << 6) 155 #define M88K_N_IC_ARGS 3 156 #define M88K_INSTR_ALIGNMENT_SHIFT 2 157 #define M88K_IC_ENTRIES_SHIFT 10 158 #define M88K_IC_ENTRIES_PER_PAGE (1 << M88K_IC_ENTRIES_SHIFT) 159 #define M88K_PC_TO_IC_ENTRY(a) (((a)>>M88K_INSTR_ALIGNMENT_SHIFT) \ 160 & (M88K_IC_ENTRIES_PER_PAGE-1)) 161 #define M88K_ADDR_TO_PAGENR(a) ((a) >> (M88K_IC_ENTRIES_SHIFT \ 162 + M88K_INSTR_ALIGNMENT_SHIFT)) 166 #define M88K_MAX_VPH_TLB_ENTRIES 128 169 #define N_M88K_REGS 32 172 #define M88K_ZERO_REG 0 173 #define M88K_RETURN_REG 1 175 #define M88K_CMP_HS 0x00000800 176 #define M88K_CMP_LO 0x00000400 177 #define M88K_CMP_LS 0x00000200 178 #define M88K_CMP_HI 0x00000100 179 #define M88K_CMP_GE 0x00000080 180 #define M88K_CMP_LT 0x00000040 181 #define M88K_CMP_LE 0x00000020 182 #define M88K_CMP_GT 0x00000010 183 #define M88K_CMP_NE 0x00000008 184 #define M88K_CMP_EQ 0x00000004 187 #define M88K_EXCEPTION_RESET 0 188 #define M88K_EXCEPTION_INTERRUPT 1 189 #define M88K_EXCEPTION_INSTRUCTION_ACCESS 2 190 #define M88K_EXCEPTION_DATA_ACCESS 3 191 #define M88K_EXCEPTION_MISALIGNED_ACCESS 4 192 #define M88K_EXCEPTION_UNIMPLEMENTED_OPCODE 5 193 #define M88K_EXCEPTION_PRIVILEGE_VIOLATION 6 194 #define M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION 7 195 #define M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE 8 196 #define M88K_EXCEPTION_INTEGER_OVERFLOW 9 197 #define M88K_EXCEPTION_ERROR 10 198 #define M88K_EXCEPTION_SFU1_PRECISE 114 199 #define M88K_EXCEPTION_SFU1_IMPRECISE 115 200 #define M88K_EXCEPTION_USER_TRAPS_START 128 203 #define M88K_PROM_INSTR 0xf400fc92 210 #define MAX_M8820X_CMMUS 8 211 #define M8820X_LENGTH 0x1000 212 #define N_M88200_BATC_REGS 10 213 #define N_M88200_PATC_ENTRIES 56 214 #define M8820X_PATC_SUPERVISOR_BIT 0x00000001 221 int patc_update_index;
278 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
282 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
291 uint64_t *return_addr,
int flags);
void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr)
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
void m88k_exception(struct cpu *cpu, int vector, int is_trap)
#define N_M88200_BATC_REGS
void m88k_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
int m88k_cpu_family_init(struct cpu_family *)
#define DYNTRANS_ITC(arch)
void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr)
#define N_M88200_PATC_ENTRIES
#define N_M88K_CONTROL_REGS
int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define VPH32EXTENDED(arch, ARCH, ex)
void m88k_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
#define VPH_TLBS(arch, ARCH)
int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
int m88k_run_instr(struct cpu *cpu)
int m88k_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte)
void m88k_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define VPH32(arch, ARCH)
#define N_M88K_FPU_CONTROL_REGS